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publication number s25fl116k_00 revision 06 issue date november 6, 2013 s25fl116k s25fl116k cover sheet 16-mbit (2-mbyte) cmos 3.0-vo lt flash non-volatile memory serial peripheral interface (spi) with multi-i/o and industrial and automotive temperature data sheet (preliminary) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary s tatus of this document indicates that product qual- ification has been completed, and that initial production has begun. due to the phases of the manufacturing process that requir e maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. publication number s25fl116k_00 revision 06 issue date november 6, 2013 features ? serial peripheral interface (spi) ? spi clock polarity and phase modes 0 and 3 ? command subset and footprint compatible with s25fl016k ? read ? normal read (serial): 50 mhz clock rate ? fast read (serial): 108 mhz clock rate ? dual / quad (multi-i/o) read 108 mhz clock rate ? 54 mb/s maximum continuous data transfer rate ? efficient execute-in-place (xip) ? continuous and wrapped read modes ? serial flash discoverable parameters (sfdp) ? program ? serial-input page program (up to 256 bytes) ? program suspend and resume ? erase ? uniform sector erase (4 kb) ? uniform block erase (64 kb) ? bulk erase ? erase suspend and resume ? cycling endurance ? 100k program-erase cycles on any sector, minimum ? data retention ? 20-year data retention, typical ? security ? three 256-byte security registers with otp protection ? low supply voltage protection of the entire memory ? top / bottom relative block protection range, 4 kb to all of memory ? 8-byte unique id for each device ? non-volatile status register bits control protection modes ? software command protection ? hardware input signal protection ? lock-down until power cycle protection ? otp protection of security registers ? 90 nm floating gate technology ? single supply voltage: 2.7v to 3.6v ? temperature ranges ? industrial (?40c to +85c) ? automotive (?40c to +105c) ? package options ? s25fl116k ? 8-lead soic (150 mil) - soa008 ? 8-lead soic (208 mil) - soc008 ? 8-contact wson 5x6 - wnd008 ? 24-ball bga 6 mm x 8 mm - fab024 and fac024 ?kgd / kgw s25fl116k 16-mbit (2-mbyte) cmos 3.0-vo lt flash non-volatile memory serial peripheral interface (spi) with multi-i/o and industrial and automotive temperature data sheet (preliminary)
4 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 1. performance summary table 1.1 maximum read rates (v cc = 2.7v to 3.6v, 105c) command clock rate (mhz) mbytes/s read 50 6.25 fast read 108 13.5 dual read 108 27 quad read 108 54 table 1.2 typical program and erase rates (v cc = 2.7v to 3.6v, 105c) operation kbytes/s page programming (256-byte page buffer) 365 4-kbyte sector erase 58 64-kbyte sector erase 131 table 1.3 typical current consumption (v cc = 2.7v to 3.6v, 105c) operation current (ma) serial read 50 mhz 7 serial read 108 mhz 12 dual read 108 mhz 14 quad read 108 mhz 16 program 20 erase 20 standby 0.015 deep-power down 0.002
november 6, 2013 s25fl116k_00_06 s25fl116k 5 data sheet (preliminary) table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. performance summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 migration notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 other resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 hardware interface 3. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 3.1 input / output summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 address and data configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 chip select (cs#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 serial input (si) / io0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 serial output (so) / io1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 write protect (wp#) / io2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 hold# / io3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 core and i/o signal voltage supply (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 supply and signal ground (v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.11 not connected (nc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.12 reserved for future use (rfu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.13 do not use (dnu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.14 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. signal protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 spi clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 command protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 interface states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4 status register effects on the interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.5 data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4 ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.5 power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.6 power on (cold) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.7 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6. physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2 physical diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 software interface 7. address space maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2 flash memory array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.3 security registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.4 status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.5 device identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.1 spi operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.2 write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.3 status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1 configuration and status commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.2 program and erase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 9.3 read commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.4 id and security commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10. data integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.1 endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.2 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ordering information 11. ordering part number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12. contacting spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 13. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
november 6, 2013 s25fl116k_00_06 s25fl116k 7 data sheet (preliminary) figures figure 3.1 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3.2 bus master and memory devices on the spi bus ? single bit data path. . . . . . . . . . . . . . . 17 figure 3.3 bus master and memory devices on the spi bus ? dual bit data path . . . . . . . . . . . . . . . . 17 figure 3.4 bus master and memory devices on the spi bus ? quad bit data path . . . . . . . . . . . . . . . 18 figure 4.1 spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4.2 stand alone instruction command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 4.3 single bit wide input command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 4.4 single bit wide output command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 4.5 single bit wide i/o command without latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 4.6 single bit wide i/o command with latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 figure 4.7 dual output command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 4.8 quad output command without latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 figure 4.9 dual i/o command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 4.10 quad i/o command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 5.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 5.2 maximum positive overshoot wavefo rm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 5.3 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5.4 input, output, and timing reference levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5.5 power-up timing and voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 5.6 power-down and voltage drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 5.7 clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 5.8 spi single bit input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 5.9 spi single bit output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 5.10 spi mio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 5.11 hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 5.12 wp# input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 9.1 read status register command sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 9.2 write enable (wren 06h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 9.3 write enable for volatile st atus register command sequence . . . . . . . . . . . . . . . . . . . . . . 57 figure 9.4 write disable (wrdi 04h) command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 9.5 write status registers command sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 9.6 page program command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 figure 9.7 sector erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 9.8 64 kb block erase command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 9.9 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 9.10 erase / program suspend command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 9.11 erase / program resume command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 9.12 read data command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 9.13 fast read command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 9.14 fast read dual output command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 9.15 fast read quad output command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 9.16 fast read dual i/o command seq uence (initial command or previous m5-4 10) . . . . . . . 66 figure 9.17 fast read dual i/o command sequence (previ ous command set m5-4 = 10) . . . . . . . . . . 66 figure 9.18 fast read quad i/o command se quence (initial command or previous m5-4 10) . . . . . . 67 figure 9.19 fast read quad i/o command sequence (previous command set m5-4 = 10). . . . . . . . . . 67 figure 9.20 set burst with wrap command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 9.21 continuous read mode reset for fast read dual or quad i/o . . . . . . . . . . . . . . . . . . . . . . 69 figure 9.22 deep power-down command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 9.23 release from deep-power-down command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 9.24 read electronic signature (res abh) command seq uence . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 9.25 read_id (90h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 figure 9.26 read jedec id command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 9.27 read sfdp register command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 9.28 erase security registers command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) figure 9.29 program security registers command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 9.30 read security registers command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
november 6, 2013 s25fl116k_00_06 s25fl116k 9 data sheet (preliminary) tables table 1.1 maximum read rates (v cc = 2.7v to 3.6v, 105c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1.2 typical program and erase rates (v cc = 2.7v to 3.6v, 105c) . . . . . . . . . . . . . . . . . . . . . . . 4 table 1.3 typical current consumption (v cc = 2.7v to 3.6v, 105c). . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2.1 fl generations comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3.1 signal list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4.1 interface states summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5.2 latchup specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5.3 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5.4 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5.5 ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5.6 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5.7 power-up timing and voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5.8 industrial temperature ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 6.1 8-connector package, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 6.2 24-ball bga, 5x5 ball footprint (fab024), top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 6.3 24-ball bga, 4x6 ball footprint (fac024), top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 7.1 s25fl116k main memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 7.2 security register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 7.3 serial flash discoverable parameter definition table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 7.4 status register-1 (sr1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 7.5 status register-2 (sr2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 7.6 status register-3 (sr3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 7.7 fl116k block protection (cmp = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 7.8 fl116k block protection (cmp = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 7.9 status register protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 7.10 latency cycles versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 7.11 device identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 9.1 command set (configuration, status, erase, program commands (1) ) . . . . . . . . . . . . . . . . 54 table 9.2 command set (read commands). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 9.3 command set (id, security commands). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 9.4 commands accepted during suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 10.1 erase endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 11.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 2. general description the s25fl116k of the fl1-k family non-volatile flash me mory devices connect to a host system via a serial peripheral interface (spi). traditional spi single bit serial input and output (single i/o or sio) is supported as well as optional two bit (dual i/o or dio) and four bit (q uad i/o or qio) serial protocols. this multiple width interface is called spi multi-i/o or mio. the spi-mio protocols use only 4 to 6 signals: ? chip select (cs#) ? serial clock (clk) ? serial data ? io0 (si) ? io1 (so) ? io2 (wp#) ? io3 (hold#) the sio protocol uses serial input (si) and serial ou tput (so) for data transfer . the dio prot ocols use io0 and io1 to input or ou tput two bits of data in each clock cycle. the write protect (wp#) input signal option allows hardwar e control over data protec tion. software controlled commands can also manage data protection. the hold# input signal option allows commands to be suspend ed and resumed on any clock cycle. the qio protocols use all of the data signals (io0 to io 3) to transfer 4 bits in ea ch clock cycle. when the qio protocols are enabled the wp# and hold # inputs and features are disabled. clock frequency of up to 108 mhz is supported, allowing data transfer rates up to: ? single bit data path = 13.5 mbytes/s ? dual bit data path = 27 mbytes/s ? quad bit data path = 54 mbytes/s executing code directly from flash memory is often called execute-in-place or xip. by using s25fl116k devices at the higher clock rates supported, with qio commands, the command read transfer rate can match or exceed traditional x8 or x16 parallel interface, a synchronous, nor flash memories, while reducing signal count dramatically. the continuous read mode allows for random memory access with as few as 8-clocks of overhead for each access, providing efficient xip oper ation. the wrapped read mode provides efficient instruction or data cache refill via a fast read of the crit ical byte that causes a cache miss, followed by reading all other bytes in the same cache line in a single read command. the s25fl116k: ? support jedec standard manufacturer and device type identification. ? program pages of 256 bytes each. one to 256 bytes ca n be programmed in each page program operation. pages can be erased in groups of 16 (4-kb align ed sector erase), groups of 256 (64-kb aligned block erase), or the entire chip (chip erase). ? the s25fl116k operates on a single 2.7v to 3.6v power supply and all devices are offered in space- saving packages. ? provides an ideal storage solution for systems with limited space, signal connections, and power. these memories offer flexibility and performance well beyond ordinary serial flash devices. they are ideal for code shadowing to ram, executing code dire ctly (xip), and storing reprogrammable data.
november 6, 2013 s25fl116k_00_06 s25fl116k 11 data sheet (preliminary) 2.1 migration notes 2.1.1 features comparison the s25fl1-k (s25fl116k, s25fl132k , and s25fl164k) is command set and footprint compatible with prior generation fl-k and fl-p families. notes: 1. s25fl-k family devices can erase 4-kb sectors in groups of 32 kb or 64 kb. 2. s25fl1-k family devices can erase 4-kb sectors in groups of 64 kb. 3. s25fl-p has either 64-kb or 256-kb uniform sectors depending on an ordering option. 4. refer to individual data sheets for further details. 2.1.2 known feature differences from prior generations 2.1.2.1 secure silicon region (otp) the size and format (address map) of the one time program area is the same for the s25fl1-k and the s25fl-k but different for the s25fl-p. 2.1.2.2 commands not supported the following s25fl-k and s25fl- p commands are not supported: ? quad page pgm (32h) ? half-block erase 32k (52h) ? word read quad i/o (e7) ? octal word read quad i/o (e3h) ? mfid dual i/o (92h) ? mfid quad i/o (94h) ? read unique id (4bh) table 2.1 fl generations comparison parameter s25fl1-k s25fl-k s25fl-p technology node 90 nm 90 nm 90 nm architecture floating gate floating gate mirrorbit ? release date in production in production in production density 16 mbit - 64 mbit 4 mbit - 128 mbit 32 mbit - 256 mbit bus width x1, x2, x4 x1 , x2, x4 x1, x2, x4 supply voltage 2.7v - 3.6v 2.7v - 3.6v 2.7v - 3.6v normal read speed 6 mb/s (50 mhz) 6 mb/s (50 mhz) 5 mb/s (40 mhz) fast read speed 13.5 mb/s (108 mhz) 13 mb/s (104 mhz) 13 mb/s (104 mhz) dual read speed 27 mb/s (108 mhz) 26 mb/s (104 mhz) 20 mb/s (80 mhz) quad read speed 54 mb/s (108 mhz) 52 mb/s (104 mhz) 40 mb/s (80 mhz) program buffer size 256b 256b 256b page programming time (typ.) 700 s (256b) 700 s (256b) 1500 s (256b) program suspend / resume yes yes no erase sector size 4 kb / 64 kb 4 kb / 32 kb / 64 kb 64 kb / 256 kb parameter sector size n/a n/a 4 kb sector erase time (typ.) 70 ms (4 kb), 350 ms (64 kb) 30 ms (4 kb), 150 ms (64 kb) 500 ms (64 kb) erase suspend / resume yes yes no otp size 768b (3 x 256b) 768b (3 x 256b) 506b operating temperature ?40c to +85c / +105c ?40c to +85c ?40c to +85c / +105c
12 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 2.1.2.3 new features the s25fl116k introduces new features to low density spi category memories: ? variable read latency (number of dummy cycles) for fast er initial access time or higher clock rate read commands ? automotive temperature range ? volatile configuration option in additi on to legacy non-volatile configuration 2.2 glossary ? command = all information transferred between the host system and memory during one period while cs# is low. this includes the instruction (sometimes called an operation code or opcode) and any required address, mode bits, latency cycles, or data. ? flash = the name for a type of electrical erase prog rammable read only memory (eeprom) that erases large blocks of memory bits in parallel, making the erase operati on much faster than early eeprom. ? high = a signal voltage level v ih or a logic level representing a binary one (1). ? instruction = the 8-bit code indicating the function to be performed by a command (sometimes called an operation code or opcode). t he instruction is always the first 8 bi ts transferred from host system to the memory in any command. ? low = a signal voltage level v il or a logic level representing a binary zero (0). ? lsb = least significant bit = generally the right most bi t, with the lowest order of magnitude value, within a group of bits of a register or data value. ? msb = most significant bit = generally the left most bit, with the highes t order of magnitude value, within a group of bits of a register or data value. ? non-volatile = no power is needed to maintain data stored in the memory. ? opn = ordering part number = the alphanumeric string specifying the memory device type, density, package, factory non-volatile configuration, etc. used to select the desired device. ? page = 256-byte aligned and length group of data. ? pcb = printed circuit board. ? register bit references = are in the format: regi ster_name[bit_number] or register_name[bit_range_msb: bit_range_lsb]. ? sector = erase unit size; all sectors are physically 4- kbytes aligned and length. depending on the erase command used, groups of physical sectors may be eras ed as a larger logical sector of 64 kbytes. ? write = an operation that changes data within volatile or non-volatile registers bits or non-volatile flash memory. when changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data is done, as part of the operation, such that the non-volatile data is modified by the write operation, in the same way that volatile data is modified ? as a single operation. the non-volatile data appears to the host system to be updated by the single write command, without the need for separate commands for erase and reprogram of adjacent, but unaffected data.
november 6, 2013 s25fl116k_00_06 s25fl116k 13 data sheet (preliminary) 2.3 other resources 2.3.1 links to software http://www.spansion.com/ support/pages/support.aspx 2.3.2 links to application notes http://www.spansion.com/support/technical documents/pages/applicationnotes.aspx 2.3.3 specification bulletins specification bulletins provide information on temporar y differences in feature description or parametric variance since the publication of the last full data sheet. contact your local sales office for details. obtain the latest list of company locations and contact information at: http://www.spansion.com/about/pages/locations.aspx
14 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) hardware interface serial peripheral interface with multiple input / output (spi-mio) many memory devices connect to their host system with separate parallel control, address, and data signals that require a large number of signal connections and la rger package size. the large number of connections increase power consumption due to so many signals switching and the larger package increases cost. the s25fl116k reduces the number of signals for connecti on to the host system by serially transferring all control, address, and data information over 4 to 6 si gnals. this reduces the cost of the memory package, reduces signal switching power, and either reduces the host connection count or frees host connectors for use in providing other features. the s25fl116k uses the industry standard single bit seri al peripheral interface (spi) and also supports commands for two bit (dual) and four bit (quad) wide serial transfers. this multiple width interface is called spi multi-i/o or spi-mio. 3. signal descriptions 3.1 input / output summary note: 1. a signal name ending with the # symbol is active when low. table 3.1 signal list signal name type description sck input serial clock. cs# input chip select. si (io0) i/o serial input for single bit data commands. io0 for dual or quad commands. so (io1) i/o serial output for single bit data commands. io1 for dual or quad commands. wp# (io2) i/o write protect in single bit or dual data commands . io2 in quad mode. the signal has an internal pull-up resistor and may be left un connected in the host system if not used for quad commands. hold# (io3) i/o hold (pause) serial transfer in single bit or dual data commands. io3 in quad-i/o mode. the signal has an internal pull-up resistor and may be left unconnected in the host system if not used for quad commands. v cc supply core and i/o power supply. v ss supply ground. nc unused not connected. no device internal signal is connec ted to the package connector nor is there any future plan to use the connecto r for a signal. the connection may safely be used for routing space for a signal on a printe d circuit board (pcb). however, any signal connected to an nc must not have voltage levels higher than v cc . rfu reserved reserved for future use. no device internal signal is currently connected to the package connector but there is potential future use of the connector for a signal. it is recommended to not use rfu connectors for pcb routing channels so that the pcb may take advantage of future enhanced features in compatible footprint devices. dnu reserved do not use. a device internal signal may be c onnected to the package connector. the connection may be used by spansion ? for test or other purposes and is not intended for connection to any host system signal. any dnu si gnal related function will be inactive when the signal is at v il . the signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to this connection.
november 6, 2013 s25fl116k_00_06 s25fl116k 15 data sheet (preliminary) 3.2 address and data configuration traditional spi single bit wide commands (single or sio) send information from the host to the memory only on the si signal. data may be sent back to the host serially on the serial output (so) signal. dual or quad output commands send information from th e host to the memory only on the si signal. data will be returned to the host as a sequence of bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io3. dual or quad input / output (i/o) commands send informa tion from the host to the memory as bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io3. data is returned to the host similarly as bit pairs on io0 and io1 or four bit (nibble) groups on io0, io 1, io2, and io3. 3.3 serial clock (sck) this input signal provides the synchronization reference fo r the spi interface. instructions, addresses, or data input are latched on the rising edge of the sck signal. data output changes after the falling edge of sck. 3.4 chip select (cs#) the chip select signal indicates when a command for the device is in process and the other signals are relevant for the memory device. when the cs# signal is at the logic high state, the device is not selected and all input signals are ignored and all output signals are high impedance. unless an internal program, erase or write status registers embedded operat ion is in progress, the device will be in the standby power mode. driving the cs# input to logic low st ate enables the device, placing it in the active power mode. after power- up, a falling edge on cs# is required prior to the start of any command. 3.5 serial input (si) / io0 this input signal is used to transfer data serially into the device. it receives instructions, addresses, and data to be programmed. values are latched on the rising edge of serial sck clock signal. si becomes io0 - an input and output during dual and quad commands for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial sck clock signal) as well as shifting out data (on the falling edge of sck). 3.6 serial output (so) / io1 this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of the serial sck clock signal. so becomes io1, an input and output during dual and quad commands for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial sck clock signal) as well as shifting out data (on the falling edge of sck). 3.7 write protect (wp#) / io2 when wp# is driven low (v il ), while the status register protect bits (srp1 and srp0) of the status registers (sr2[0] and sr1[7]) are set to 0 and 1 respecti vely, it is not possible to write to the status registers. this prevents any alteration of the status registers. as a consequence, all the data bytes in the memory area that are protected by th e block protect, tb, sec, and cmp bits in the status registers, are also hardware protected against data modification while wp# remains low. the wp# function is not available when the quad mode is enabled (qe) in status register-2 (sr2[1]=1). the wp# function is replaced by io2 for input and output during quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of t he sck signal) as well as shifting out data (on the falling edge of sck). wp# has an internal pull-up resistanc e; when unconnected, wp# is at v ih and may be left unconnected in the host system if not used for quad mode.
16 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 3.8 hold# / io3 the hold# signal is used to pause any serial communi cations with the device without deselecting the device or stopping the serial clock. to enter the hold condition, the devi ce must be selected by driving the cs # input to the logic low state. it is required that the user keep the cs# input low state during the entire duration of the hold condition. this is to ensure that the state of the interface logic remain s unchanged from the moment of entering the hold condition. the hold condition starts on the falling edge of the ho ld (hold#) signal, provided that this coincides with sck being at the logic low state. if the falling edge does not coincide with the sck signal being at the logic low state, the hold condition starts whenever the sck signal reaches the logic low state. taking the hold# signal to the logic low state does not terminate any writ e, program or erase operation that is currently in progress. during the hold condition, so is in high imped ance and both the si and sck input are don't care. the hold condition ends on the rising edge of the hold (hold#) signal, provided that this coincides with the sck signal being at the logic low state. if the rising edge does not coincide with the sck signal being at the logic low state, the hold condition ends whenever the sck signal reaches the logic low state. figure 3.1 hold condition 3.9 core and i/o signal voltage supply (v cc ) v cc is the voltage source for all device internal logic and input / output signals. it is the single voltage used for all device functions including read, program, and erase. 3.10 supply and signal ground (v ss ) v ss is the common voltage drain and ground reference fo r the device core, input signal receivers, and output drivers. 3.11 not connected (nc) no device internal signal is connected to the pack age connector nor is there any future plan to use the connector for a signal. the connection may safely be us ed for routing space for a signal on a printed circuit board (pcb). 3.12 reserved for future use (rfu) no device internal signal is currently connected to th e package connector but is there potential future use for the connector for a signal. it is recommended to not us e rfu connectors for pcb r outing channels so that the pcb may take advantage of future enhanced fe atures in compatible footprint devices. cs# sclk hold# si_or_io_(during_input) so_or_io_(internal) so_or_io_(external) valid input don?t care valid input don?t care valid input a b c d e a b b c d e hold condition standard use hold condition non-standard use
november 6, 2013 s25fl116k_00_06 s25fl116k 17 data sheet (preliminary) 3.13 do not use (dnu) a device internal signal may be connected to the package connector. the connection may be used by spansion for test or other purposes and is not inte nded for connection to any host system signal. any dnu signal related function will be inactive when the signal is at v il . the signal has an internal pull-down resistor and may be left unconn ected in the host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to these connections. 3.14 block diagrams figure 3.2 bus master and memory devices on the spi bus ? single bit data path figure 3.3 bus master and memory devices on the spi bus ? dual bit data path s pi b us m as ter hold# wp# s o s i s ck c s 2# c s 1# s pi fl as h s pi fl as h hold# wp# s o s i s ck c s 2# c s 1# s pi b us m as ter hold# wp# io1 io0 s ck c s 2# c s 1# s pi fl as h s pi fl as h hold# wp# io0 io1 s ck c s 2# c s 1#
18 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) figure 3.4 bus master and memory devices on the spi bus ? quad bit data path s pi b us m as ter io 3 io2 io1 io0 s ck c s 2# c s 1# s pi fl as h s pi fl as h io 3 io2 io0 io1 s ck c s 2# c s 1#
november 6, 2013 s25fl116k_00_06 s25fl116k 19 data sheet (preliminary) 4. signal protocols 4.1 spi clock modes the s25fl116k can be driven by an embedded microcontro ller (bus master) in either of the two following clocking modes. ? mode 0 with clock polarity (cpol) = 0 and, clock phase (cpha) = 0 ? mode 3 with cpol = 1 and, cpha = 1 for these two modes, input data into the device is always latched in on the rising edge of the sck signal and the output data is always available from the falling edge of the sck clock signal. the difference between the two modes is the clock polari ty when the bus master is in standby mode and not transferring any data. ? sck will stay at logic low state with cpol = 0, cpha = 0 ? sck will stay at logic high state with cpol = 1, cpha = 1 figure 4.1 spi modes supported timing diagrams throughout the remainder of the docu ment are generally shown as both mode 0 and 3 by showing sclk as both high and low at the fall of cs#. in some cases a timing diagram may show only mode 0 with sclk low at the fall of cs#. in such a case, mode 3 timing simply means clock is high at the fall of cs# so no sclk rising edge set up or hold time to the falling edge of cs# is needed for mode 3. sclk cycles are measured (counted) from one falling edge of sclk to the next falling edge of sclk. in mode 0 the beginning of the first sclk cycle in a comman d is measured from the falling edge of cs# to the first falling edge of sclk because sclk is already low at the beginning of a command. 4.2 command protocol all communication between the host system and s25fl11 6k is in the form of units called commands. all commands begin with an instruction that selects the ty pe of information transfer or device operation to be performed. commands may also have an address, instruct ion modifier (mode), latency period, data transfer to the memory, or data transfer from the memory. all instruction, address, and data information is transferred serially between the host system and memory device. all instructions are transferred from host to memory as a single bit serial sequence on the si signal. single bit wide commands may provide an address or data sent only on the si signal. data may be sent back to the host serially on the so signal. dual or quad output commands provide an address sent to the memory only on the si signal. data will be returned to the host as a sequence of bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io3. dual or quad input / output (i/o) commands provide an address sent from the host as bit pairs on io0 and io1 or, four bit (nibble) groups on io0, io1, io2, and io3. data is returned to the host similarly as bit pairs on io0 and io1 or, four bit (nibble) groups on io0, io1, io2, and io3. commands are structured as follows: ? each command begins with cs# going low and ends with cs# returning high. the memory device is selected by the host driving the chip sele ct (cs#) signal low throughout a command. cpol=0_cpha=0_sclk cpol=1_cpha=1_sclk cs# si so msb msb
20 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) ? the serial clock (sck) marks the transfer of each bit or group of bits between the host and memory. ? each command begins with an eight bit (byte) instruct ion. the instruction is always presented only as a single bit serial sequence on the serial input (si) signal with one bit transferred to the memory device on each sck rising edge. the instruction selects the type of information transfer or device operation to be performed. ? the instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces in the device . the instruction determines the ad dress space used. the address is a 24-bit, byte boundary, a ddress. the address transfers occur on sck rising edge. ? the width of all transfers following the instructio n are determined by the instruction sent. following transfers may continue to be single bit serial on only t he si or serial output (so) signals, they may be done in 2-bit groups per (dual) transfer on the io0 and io1 signals, or they may be done in 4-bit groups per (quad) transfer on the io0-io3 signals. within the dual or quad groups the least si gnificant bit is on io0. more significant bits are placed in significance order on each higher numbered io signal. single bits or parallel bit groups are transferred in most to least significant bit order. ? some instructions send an instructio n modifier called mode bits, following the address, to indicate that the next command will be of the same type with an implie d, rather than an explicit, instruction. the next command thus does not provide an instruction byte, only a new address and mode bits. this reduces the time needed to send each command when the same command type is repeated in a sequence of commands. the mode bit transfers occur on sck rising edge. ? the address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read data is returned to the host. ? write data bit transfers occur on sck rising edge. ? sck continues to toggle during any read access late ncy period. the latency may be zero to several sck cycles (also referred to as dummy cycle s). at the end of the re ad latency cycles, the first read data bits are driven from the outputs on sck falling edge at the end of the last read la tency cycle. the first read data bits are considered transferred to the host on the following sclk rising edge. each following transfer occurs on the next sck rising edge. ? if the command returns read data to the host, the devi ce continues sending data transfers until the host takes the cs# signal high. the cs# signal can be driven high after any transfer in the read data sequence. this will terminate the command. ? at the end of a command that does not return data, the host drives the cs# input high. the cs# signal must go high after the eighth bit, of a stand alone in struction or, of the last write data byte that is transferred. that is, the cs# signal must be driven high when the num ber of clock cycles after cs# signal was driven low is an exact multiple of eight cycles. if t he cs# signal does not go high exactly at the eight sclk cycle boundary of the instruction or write data, the command is reje cted and not executed. ? all instruction, address, and mode bits are shifted into the device with the most significant bits (msb) first. the data bits are shifted in and out of the device msb first. all data is transferred in byte units with the lowest address byte sent first. following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments. ? all attempts to read the flash memory array dur ing a program, erase, or a write cycle (embedded operations) are ignored. the embedded operation will co ntinue to execute without any affect. a very limited set of commands are accepted during an embedded o peration. these are discussed in the individual command descriptions. ? depending on the command, the time for execution varies. a command to read status information from an executing command is available to determine when the command completes execution and whether the command was successful.
november 6, 2013 s25fl116k_00_06 s25fl116k 21 data sheet (preliminary) 4.2.1 command sequence examples figure 4.2 stand alone instruction command figure 4.3 single bit wide input command figure 4.4 single bit wide output command figure 4.5 single bit wide i/o command without latency figure 4.6 single bit wide i/o command with latency cs# sclk si so phase 7 6 5 4 3 2 1 0 instruction cs# sclk si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data cs# sclk si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data 2 cs# sclk si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address data 1 data 2 cs# sclk si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1
22 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) figure 4.7 dual output command figure 4.8 quad output comma nd without latency figure 4.9 dual i/o command figure 4.10 quad i/o command additional sequence diagrams, specific to each command, are provided in commands on page 54 . cs# sclk io0 io1 phase 7 6 5 4 3 2 1 0 23 22 21 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 instruction address dummy data 1 data 2 cs# sclk io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 23 1 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 instruction address data 1 data 2 data 3 data 4 data 5 ... cs# sclk io0 io1 phase 7 6 5 4 3 2 1 0 22 2 0 6 4 2 0 6 4 2 0 23 3 1 7 5 3 1 7 5 3 1 instruction address dummy data 1 data 2 cs# sclk io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 20 4 0 4 4 0 4 0 4 0 4 0 21 5 1 5 5 1 5 1 5 1 5 1 22 6 2 6 6 2 6 2 6 2 6 2 23 7 3 7 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4
november 6, 2013 s25fl116k_00_06 s25fl116k 23 data sheet (preliminary) 4.3 interface states this section describes the input and output signal levels as related to the spi interface behavior. legend: z = no driver - floating signal hl = host driving v il hh = host driving v ih hv = either hl or hh x = hl or hh or z ht = toggling between hl and hh ml = memory driving v il mh = memory driving v ih mv = either ml or mh 4.3.1 low power hardware data protection when v cc is less than v wi the memory device will ignore commands to ensure that program and erase operations can not start when the core supply voltage is out of the operating range. 4.3.2 power-on (cold) reset when the core voltage supply remains at or below the v wi voltage for t pd time, then rises to v cc (minimum) the device will begin its power-on-reset (por) process. por continues until the end of t puw . during t puw the device does not react to write commands. following the end of t puw the device transitions to the interface standby state and can accept write commands. for additional information on por see power on (cold) reset on page 31 . table 4.1 interface states summary interface state v cc sclk cs# hold# / io3 wp# / io2 so / io1 si / io0 low power hardware data protection < v wi xxxxzx power-on (cold) reset v cc (min) x hh x x z x interface standby v cc (min) x x x x z x instruction cycle v cc (min) ht hl hh hv z hv hold cycle v cc (min) hv or ht hl hl x x x single input cycle host to memory transfer v cc (min) ht hl hh x z hv single latency (dummy) cycle v cc (min) ht hl hh x z x single output cycle memory to host transfer v cc (min) ht hl hh x mv x dual input cycle host to memory transfer v cc (min) ht hl hh x hv hv dual latency (dummy) cycle v cc (min) ht hl hh x x x dual output cycle memory to host transfer v cc (min) ht hl hh x mv mv quad input cycle host to memory transfer v cc (min) ht hl hv hv hv hv quad latency (dummy) cycle v cc (min) ht hl x x x x quad output cycle memory to host transfer v cc (min) ht hl mv mv mv mv
24 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 4.3.3 interface standby when cs# is high the spi interface is in standby st ate. inputs are ignored. t he interface waits for the beginning of a new command. the next interface state is instruction cycle when cs# goes low to begin a new command. while in interface standby state the memory device draws standby current (i sb ) if no embedded algorithm is in progress. if an embedded algorithm is in progre ss, the related current is drawn until the end of the algorithm when the entire device returns to standby current draw. 4.3.4 instruction cycle when the host drives the msb of an instruction and cs# goes low, on the next rising edge of sck the device captures the msb of the in struction that begins the new command. on each following rising edge of sck the device captures the next lower significance bit of the 8-bit instruction. the host keeps cs# low, hold# high, and drives write protect (wp#) signal as needed for the instruction. however, wp# is only relevant during instruction cycles of a write status re gisters command and is otherwise ignored. each instruction selects the address space that is operated on and the transfer format used during the remainder of the command. the transfer format may be si ngle, dual output, quad output, dual i/o, or quad i/o. the expected next interface stat e depends on the instruction received. some commands are stand alone, needing no address or data transfer to or from the memory. the host returns cs# high after the rising edge of sck for the eight h bit of the instruction in such commands. the next interface state in this case is interface standby. 4.3.5 hold when quad mode is not enabled (sr2[1]=0) the hold# / io3 signal is used as the hold# input. the host keeps hold# low, sclk may be at a valid level or cont inue toggling, and cs# is low. when hold# is low a command is paused, as though sck were held low. s i / io0 and so / io1 ignore the input level when acting as inputs and are high impedance when acting as outputs during hold state. whether these signals are input or output depends on the command and the point in the command sequence when hold# is asserted low. when hold# returns high the next state is the same state the interface was in just before hold# was asserted low. 4.3.6 single input cycle ? host to memory transfer several commands transfer info rmation after the instruction on the single serial input (si) signal from host to the memory device. the dual output, and quad output commands send address to the memory using only si but return read data using the i/o signals. the host keeps cs# low, hold# high, and drives si as needed for the command. the memory does not drive the serial output (so) signal. the expected next interface state depends on the instruct ion. some instructions continue sending address or data to the memory using additional single input cycles. ot hers may transition to single latency, or directly to single, dual, or quad output. 4.3.7 single latency (dummy) cycle read commands may have zero to seve ral latency cycles during which read data is read from the main flash memory array before transfer to th e host. the number of la tency cycles are determine d by the instruction. during the latency cycles, the host keeps cs# low, and hold# high. the write protect (wp#) signal is ignored. the host may drive the si signal during these cycles or the host may leave si floating. the memory does not use any data driven on si / i/o0 or other i/o signals during the latency cycles. in dual or quad read commands, the host must stop driving the i/o signals on the falling edge at the end of the last latency cycle. it is recommended that the host stop driv ing i/o signals during latency cycles so that there is suff icient time for the host drivers to turn off before th e memory begins to drive at the end of the latency cycles. this prevents driver conflict between host and me mory when the signal direction chang es. the memory does not drive the serial output (so) or i/o signals during the latency cycles. the next interface state dep ends on the command struct ure i.e. the numb er of latency cycl es, and whether the read is single, dual, or quad width.
november 6, 2013 s25fl116k_00_06 s25fl116k 25 data sheet (preliminary) 4.3.8 single output cycle ? memory to host transfer several commands transfer information back to the hos t on the single serial output (so) signal. the host keeps cs# low, and hold# high. the wr ite protect (wp#) signal is ignor ed. the memory ignores the serial input (si) signal. the me mory drives so with data. the next interface state continues to be single output cycle until the ho st returns cs# to high ending the command. 4.3.9 dual input cycle ? h ost to memory transfer the read dual i/o command transfers two address or mode bits to the memory in each cycle. the host keeps cs# low, hold# high. the write protect (wp#) signal is ignored. the host drives address on si / io0 and so / io1. the next interface state following the de livery of address and mode bits is a dual latency cycle if there are latency cycles needed or dual output cycle if no latency is required. 4.3.10 dual latency (dummy) cycle read commands may have zero to seve ral latency cycles during which read data is read from the main flash memory array before transfer to th e host. the number of la tency cycles are determine d by the instruction. during the latency cycles, the host keeps cs# low, and hold# high. the write protect (wp#) signal is ignored. the host may drive the si / io0 and so / io1 si gnals during these cycles or the host may leave si / io0 and so / io1 floating. the memory does not use any data driven on si / io0 and so / io1 during the latency cycles. the host must stop driving si / io0 and so / io1 on the falling edge at the end of the last latency cycle. it is recomm ended that the host st op driving them durin g all latency cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. this prevents driver conflict between host and memory when the signal direction changes. the memory does not drive the si / io0 and so / io1 signals during the latency cycles. the next interface state follo wing the last latency cycle is a dual output cycle. 4.3.11 dual output cycle ? memory to host transfer the read dual output and read dual i/o return data to the host two bits in each cycle. the host keeps cs# low, and hold# high. the write protect (wp#) signal is ignored. the memory drives data on the si / io0 and so / io1 signals during the dual output cycles. the next interface state continues to be dual output cycle until the host returns cs# to high ending the command. 4.3.12 quad input cycle ? host to memory transfer the read quad i/o comm and transfers four address, mode, or data bits to the memory in each cycle. the host keeps cs# low, and drives the io signals. for read quad i/o the next interface state following the delivery of address and mode bits is a quad latency cycle if there are latency cycles needed or quad output cycle if no latency is required. 4.3.13 quad latency (dummy) cycle read commands may have zero to seve ral latency cycles during which read data is read from the main flash memory array before transfer to the host. the numbe r of latency cycles are determined by the latency control in the stat us register-3 (sr3[3:0]). during the latency cycles, the host keeps cs# low. the host may drive the io signals during these cycles or the host may leave the io floating. the memory does not use any data driven on io during the latency cycles. the host must stop driving the io signals on the falling edge at the end of the last latency cycle. it is recommended that the host stop driving them during all latency cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. this prevents driver conflict between host and memory when the signal direction changes. the memory does not dr ive the io sig nals during the latency cycles. the next interface state follo wing the last latency cycle is a quad output cycle.
26 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 4.3.14 quad output cycle ? memory to host transfer the read quad output and read quad i/o return data to the host four bits in each cycle. the host keeps cs# low. the memory drives data on io 0-io3 signals during the quad out put cycles. the next interface state continues to be quad output cycle until the host returns cs# to high ending the command. 4.4 status register effects on the interface the status register-2, bit 1 (sr2[1]), selects whethe r quad mode is enabled to ignore hold# and wp# and allow read quad output, and read quad i/o commands. 4.5 data protection some basic protection against unint ended changes to stored data are provided and controlled purely by the hardware design. these are described below. other software managed protection methods are discussed in the software section of this document. 4.5.1 low power when v cc is less than v wi the memory device will ignore commands to ensure that program and erase operations can not start when the core supply voltage is out of the operating range. 4.5.2 power-up program and erase operations continue to be prevented during the power-up to write delay (t puw ) because no write command is accepted until after t puw . 4.5.3 deep-power-down (dpd) in dpd mode the device responds only to the resume from dpd command (res abh). all other commands are ignored during dpd mode, thereby protecting the memory from program and erase operations. 4.5.4 clock pulse count the device verifies that all program, erase, and writ e status registers commands consist of a clock pulse count that is a multiple of eight before executing them. a command not having a multiple of 8 clock pulse count is ignored and no error st atus is set for the command.
november 6, 2013 s25fl116k_00_06 s25fl116k 27 data sheet (preliminary) 5. electrical characteristics 5.1 absolute maximum ratings notes: 1. this device has been designed and tested for the specified operat ion ranges. proper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may affect device reliab ility. exposure beyond absolute maximum ratings may cause permanen t damage. 2. compliant with jedec standard j-std-20c for small body sn-pb or pb-free (green) assembly and the european directive on restrictions on hazardous s ubstances (rohs) 2002/95/eu. 3. jedec std jesd22-a114a (c1=100 pf, r1=1500 ohms, r2=500 ohms). 5.1.1 input si gnal overshoot during dc conditions, input or i/o signals should remain equal to or between v ss and v cc . during voltage transitions, inputs or i/os may overshoot v ss to negative v iot or overshoot to positive v iot , for periods up to 20 ns. figure 5.1 maximum negative overshoot waveform figure 5.2 maximum positive overshoot waveform table 5.1 absolute maximum ratings parameters (1) symbol conditions range unit supply voltage v cc ?0.6 to +4.0 v voltage applied to any pin v io relative to ground ?0.6 to +4.0 v transient voltage on any pin v iot < 20 ns transient relative to ground ?2.0 to 6.0 v storage temperature t stg ?65 to +150 c lead temperature t lead (2) c electrostatic discharge voltage v esd human body model (3) ?2000 to +2000 v v il v iot < 20 n s < 20 n s < 20 n s v ih v iot < 20 n s < 20 n s < 20 n s
28 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 5.1.2 latchup characteristics note: 1. excludes power supply v cc . test conditions: v cc = 3.0 v, one connection at a time tested, connections not being tested are at v ss . 5.2 operating ranges operating ranges define those limits between wh ich functionality of the device is guaranteed. note: 1. v cc voltage during read can operate across the min and max range but should not exceed 10% of the voltage used during programming or erase of the data being read. 5.3 dc electrical characteristics notes: 1. tested on sample basis and specified thro ugh design and characterization data. t a = 25c, v cc = 3v. 2. checker board pattern. table 5.2 latchup specification description min max unit input voltage with respect to v ss on all input only connections ? 1.0 v cc + 1.0 v input voltage with respect to v ss on all i/o connections ? 1.0 v cc + 1.0 v v cc current ? 100 +100 ma table 5.3 operating ranges parameter symbol conditions spec unit min max ambient temperature t a industrial ?40 +85 c automotive ?40 +105 c supply voltage v cc full range, automotive temp 2.7 3.6 v table 5.4 dc electrical characteristics parameter symbol conditions min typ max unit input leakage i li 2 a i/o leakage i lo 2 a standby current i cc1 cs# = v cc , v in = gnd or v cc 15 25 a power-down current i cc2 cs# = v cc , v in = gnd or v cc 25a current: read single / dual / quad 1 mhz (2) i cc3 sck = 0.1 v cc / 0.9 v cc so = open 4/5/6 6/7.5/9 ma current: read single / dual / quad 33 mhz (2) i cc3 sck = 0.1 v cc / 0.9 v cc so = open 6/7/8 9/10.5/12 ma current: read single / dual / quad 50 mhz (2) i cc3 sck = 0.1 v cc / 0.9 v cc so = open 7/8/9 10/12/13.5 ma current: read single / dual / quad 108 mhz (2) i cc3 sck = 0.1 v cc / 0.9 v cc so = open 12/14/16 18/22/25 ma current: write status registers i cc4 cs# = v cc 812ma current page program i cc5 cs# = v cc 20 25 ma current sector / block erase i cc6 cs# = v cc 20 25 ma current chip erase i cc7 cs# = v cc 20 25 ma input low voltage v il -0.5 v cc x 0.2 v input high voltage v ih v cc x 0.7 v cc + 0.4 v output low voltage v ol i ol = 100 a v ss 0.2 v i ol = 1.6 ma v ss 0.4 output high voltage v oh i oh = ?100 a v cc ? 0.2 v cc v
november 6, 2013 s25fl116k_00_06 s25fl116k 29 data sheet (preliminary) 5.3.1 active power and standby power modes the device is enabled and in the active power mode when chip select (cs#) is low. when cs# is high, the device is disabled, but may still be in an active power mode until all program, er ase, and write operations have completed. the device then goes into the stand by power mode, and power consumption drops to i sb . 5.4 ac measurement conditions figure 5.3 test setup notes: 1. output high-z is defined as the point where data is no longer driven. 2. input slew rate: 1.5 v/ns. 3. ac characteristics tables assume clock and data signals have the same slew rate (slope). figure 5.4 input, output, and timing reference levels 5.4.1 capacitance characteristics notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. table 5.5 ac measurement conditions symbol parameter min max unit c l load capacitance 30 pf tr, tf input rise and fall times 2.4 ns input pulse voltage 0.2 x v cc to 0.8 v cc v input timing ref voltage 0.5 v cc v output timing ref voltage 0.5 v cc v device under te s t c l v cc + 0.4v 0.7 x v cc 0. 3 x v cc - 0.5v timing reference level 0.5 x v cc v cc 0.2v to 0.4v inp u t level s o u tp u t level s v cc - 0.2v v ss table 5.6 capacitance parameter test conditions min max unit c in input capacitance (applies to sck, cs#) 1 mhz 8 pf c out output capacitance (applies to all i/o) 1 mhz 8 pf
30 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 5.5 power-up timing note: 1. these parameters are characterized only. figure 5.5 power-up timing and voltage levels figure 5.6 power-down and voltage drop table 5.7 power-up timing and voltage levels parameter symbol spec unit min max v cc (min) to cs# low t vsl 10 s time delay before write command t puw 1 10 ms write inhibit threshold voltage v wi 1.0 2.0 v v dd (low) time t pd 10.0 s v cc time re s et s t a te re a d in s tr u ction s a llowed device i s f u lly a cce ss i b le progr a m, er as e, a nd write in s tr u ction s a re ignored c s # m us t tr a ck v cc t puw t v s l v cc (m a x) v wi v cc (min) t pd no device acce ss allowed t v s l device re a d allowed v cc (m a x) v wi time v cc (min) v cc
november 6, 2013 s25fl116k_00_06 s25fl116k 31 data sheet (preliminary) 5.6 power on (cold) reset the device executes a power-on-reset (por) process until a time delay of t puw has elapsed after the moment that v cc rises above the v wi threshold. see figure 5.5 on page 30 , figure 5.6 on page 30 , and table 5.7 on page 30 . the device must not be selected (cs# to go high with v cc ) until after (t vsl ), i.e. no commands may be sent to the device until the end of t vsl . 5.7 ac electrical characteristics table 5.8 industrial temperature ranges (sheet 1 of 2) description symbol alt spec unit min typ max clock frequency for all spi commands except for read data command (03h) and fast read command (0bh) 2.7v-3.6v v cc f r f c d.c. 108 mhz clock frequency for read data command (03h) f r d.c. 50 mhz clock frequency for all fast read commands sio and mio f fr d.c. 108 mhz clock period p sck 9.25 ns clock high, low time for f fr t clh , t cll (1) t ch , t cl 3.3 ns clock high, low time for f r t clh , t cll (1) t ch , t cl 4.3 ns clock high, low time for f r t crlh , t crll (1) t ch , t cl 6 ns clock rise time t clch (2) t crt 0.1 v/ns clock fall time t chcl (2) t cft 0.1 v/ns cs# active setup time relative to clk t slch t css 5 ns cs# not active hold time relative to clk t chsl t csh 5 ns data in setup time t dvch t su 2 ns data in hold time t chdx t hd 5 ns cs# active hold time relative to clk t chsh t css 5 ns cs# not active setup time relative to clk t shch t csh 5 ns cs# deselect time (for array read -> array read) t shsl1 t cs1 7 ns cs# deselect time (for erase or program -> read status registers) volatile status register write time t shsl2 t cs2 40 40 ns cs# deselect time (for erase or program -> suspend command) t shsl3 t cs3 130 ns output disable time t shqz (2) t dis 7 ns clock low to output valid, 30 pf, 2.7v - 3.6v t clqv1 t v1 7 ns clock low to output valid, 15 pf, 2.7v - 3.6v t clqv1 t v1 6 ns clock low to output valid (for read id commands) 2.7v - 3.6v t clqv2 t v2 8.5 ns output hold time t clqx t ho 2 ns hold# active setup time relative to clk t hlch 5 ns hold# active hold time relative to clk t chhh 5 ns hold# not active setup time relative to clk t hhch 5 ns hold# not active hold time relative to clk t chhl 5 ns hold# to output low-z t hhqx (2) t lz 7 ns hold# to output high-z t hlqz (2) t hz 12 ns write protect setup time before cs# low t whsl (3) t wps 20 ns write protect hold time after cs# high t shwl (3) t wph 100 ns cs# high to power-down mode t dp (2) 3 s cs# high to standby mode without electronic signature read t res1 (2) 3 s cs# high to standby mode with electronic signature read t res2 (2) 1.8 s
32 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and / or char acterization, not 100% tested in production. 3. only applicable as a constraint for a write status registers command when status register protect 0 (srp0) bit is set to 1. o r wpsel bit = 1. 4. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes programmed. 5. all program and erase times are tested using a random data pattern. 5.7.1 clock timing figure 5.7 clock timing 5.7.2 input / output timing figure 5.8 spi single bit input timing write status registers time t w 50 300 ms byte program time (first byte) (4)(5) t bp1 15 50 s additional byte program time (after first byte) (4)(5) t bp2 2.5 12 s page program time (5) t pp 0.7 3 ms sector erase time (4 kb) (5) t se 70 450 ms block erase time (64 kb) (5) t be2 500 2000 ms chip erase time 16 mb (5) t ce 11.2 64 s table 5.8 industrial temperature ranges (sheet 2 of 2) description symbol alt spec unit min typ max v ih (min) t ch t crt t cft t cl v cc / 2 p s ck v il (m a x) cs# sck si so msb in lsb in tcss tcss tcsh tcsh tcs tsu thd
november 6, 2013 s25fl116k_00_06 s25fl116k 33 data sheet (preliminary) figure 5.9 spi single bit output timing figure 5.10 spi mio timing figure 5.11 hold timing cs# sck si so msb out lsb out tcs tho tv tdis tlz cs# sclk io msb in lsb in msb out lsb out tcsh tcsh tcss tcss tsu thd tlz tho tcs tdis tv cs# sclk hold# si_or_io_(during_input) so_or_io_(during_output) a b b c d e thz thz tlz tlz tchhl tchhl thlch thlch tchhh tchhh thhch thhch hold condition standard use hold condition non-standard use
34 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) figure 5.12 wp# input timing cs# wp# sclk si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 write status registers instruction input data twps twph
november 6, 2013 s25fl116k_00_06 s25fl116k 35 data sheet (preliminary) 6. physical interface 6.1 connection diagrams 6.1.1 soic 8 / wson 8 6.1.2 fab024 24-ball bga 6.1.3 fac024 24-ball bga package note: 1. signal connections are in the same relative positions as fab0 24 bga, allowing a single pcb footprint to use either package. 6.1.4 special handling instru ctions for fbga packages flash memory devices in bga packages may be damage d if exposed to ultrasonic cleaning methods. the package and / or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. table 6.1 8-connector package, top view signal lead package body lead signal cs# 1 soic 8 wson 8 8vcc so / io1 2 7 hold# / io3 wp# / io2 3 6 sclk vss 4 5 si / io0 table 6.2 24-ball bga, 5x5 ball footprint (fab024), top view ball index 1 2 3 4 5 a (no ball) nc nc rfu nc b dnu sclk vss vcc nc c dnu cs# rfu wp# / io2 nc d dnu so / io1 si / io0 hold# / io3 nc e nc nc nc rfu nc table 6.3 24-ball bga, 4x6 ball fo otprint (fac024), top view ball index 1 2 3 4 a nc nc nc rfu b dnu sck vss vcc c dnu cs# rfu wp# / io2 d dnu so / io1 si / io0 hold# / io3 e nc nc nc rfu f nc nc nc nc
36 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 6.2 physical diagrams 6.2.1 soa008 ? 8-lead plastic small ou tline package (150-mils body width) g1019 \ 16-038.3f \ 10.06.11 notes: 1. all dimensions are in both inches and millmeters. 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. d and e1 dimensions are determined at datum h. 4. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outmost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash. but including any mismatch between the top and bottom of the plastic body. 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified package length. 7. the dimensions apply to the flat section of the lead between 0.10 to 0.25 mm from the lead tip. 8. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.10 mm total in excess of the "b" dimension at maximum material condition. the dambar cannot be located on the lower radius of the lead foot. 9. this chamfer feature is optional. if it is not present, then a pin 1 identifier must be located within the index area indicated. 10. lead coplanarity shall be within 0.10 mm as measured from the seating plane.
november 6, 2013 s25fl116k_00_06 s25fl116k 37 data sheet (preliminary) 6.2.2 soc008 ? 8-lead plastic small ou tline package (208-mils body width) 3 602 \ 16-0 38 .0 3 \ 9.1.6 note s : 1. all dimen s ion s are in both inche s and millmeter s . 2. dimen s ioning and tolerancing per a s me y14.5m - 1994. 3 . dimen s ion d doe s not include mold fla s h, protru s ion s or gate burr s . mold fla s h, protru s ion s or gate burr s s hall not exceed 0.15 mm per end. dimen s ion e1 doe s not include interlead fla s h or protru s ion interlead fla s h or protru s ion s hall not exceed 0.25 mm per s ide. d and e1 dimen s ion s are determined at datum h. 4. the package top may be s maller than the package bottom. dimen s ion s d and e1 are determined at the outmo s t extreme s of the pla s tic body exclu s ive of mold fla s h, tie bar burr s , gate burr s and interlead fla s h. but including any mi s match between the top and bottom of the pla s tic body. 5. datum s a and b to be determined at datum h. 6. "n" i s the maximum number of terminal po s ition s for the s pecified package length. 7. the dimen s ion s apply to the flat s ection of the lead between 0.10 to 0.25 mm from the lead tip. 8 . dimen s ion " b " doe s not include dambar protru s ion. allowable dambar protru s ion s hall be 0.10 mm total in exce ss of the " b " dimen s ion at maximum material condition. the dambar cannot be located on the lower radiu s of the lead foot. 9. thi s chamfer feature i s optional. if it i s not pre s ent, then a pin 1 identifier mu s t be located within the index area indicated. 10. lead coplanarity s hall be within 0.10 mm a s mea s ured from the s eating plane. package s oc 00 8 (inche s ) s oc 00 8 (mm) jedec s ymbol min max min max a 0.069 0.0 8 5 1.75 3 2.159 a1 0.002 0.009 8 0.051 0.249 a2 0.067 0.075 1.70 1.91 b 0.014 0.019 0. 3 56 0.4 83 b 1 0.01 3 0.01 8 0. 33 0 0.457 c 0.0075 0.0095 0.191 0.241 c1 0.006 0.00 8 0.152 0.20 3 d 0.20 8 b s c 5.2 83 b s c e 0. 3 15 b s c 8 .001 b s c e1 0.20 8 b s c 5.2 83 b s c e .050 b s c 1.27 b s c l 0.020 0.0 3 0 0.50 8 0.762 l1 .049 ref 1.25 ref l2 .010 b s c 0.25 b s c n 8 8 0? 8 ?0? 8 ? 1 5? 15? 5? 15? 2 0? 0?
38 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 6.2.3 wnd008 ? 8-c ontact wson 5x6 g1071 \ 16-038.30 \ 02.22.12 notes: 1. dimensioning and tolerancing conforms to asme y14.5m - 1994. 2. all dimensions are in millmeters. 3. n is the total number of terminals. 4 dimension ?b? applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension ?b? should not be measured in that radius area. 5 nd refers to the number of terminals on d side. 6. max. package warpage is 0.05mm. 7. maximum allowable burr is 0.076mm in all directions. 8 pin #1 id on top will be laser marked. 9 bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. symbol min nom max notes e 1.27 bsc. n 8 3 nd 4 5 l 0.55 0.60 0.65 b 0.35 0.40 0.45 4 d2 3.90 4.00 4.10 e2 3.30 3.40 3.50 d 5.00 bsc e 6.00 bsc a 0.70 0.75 0.80 a1 0.00 0.02 0.05 k 0.20 min. package wnd008
november 6, 2013 s25fl116k_00_06 s25fl116k 39 data sheet (preliminary) 6.2.4 fab024 ? 24-ball ball grid array (8 x 6 mm) package
40 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 6.2.5 fac024 ? 24-ball ball grid array (8 x 6 mm) package package fac024 jedec n/a d x e 8.00 mm x 6.00 mm nom package symbol min nom max note a --- --- 1.20 profile a1 0.25 --- --- ball height a2 0.70 --- 0.90 body thickness d 8.00 bsc. body size e 6.00 bsc. body size d1 5.00 bsc. matrix footprint e1 3.00 bsc. matrix footprint md 6 matrix size d direction me 4 matrix size e direction n 24 ball count ? b 0.35 0.40 0.45 ball diameter e 1.00 bsc. ball pitchl sd/ se 0.5/0.5 solder ball placement depopulated solder balls j package outline type 3642 f16-038.9 \ 09.10.09 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. datum c is the seating plane and is defined by the crowns of the solder balls. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10 outline and dimensions per customer requirement.
november 6, 2013 s25fl116k_00_06 s25fl116k 41 data sheet (preliminary) software interface this section discusses the features and behaviors most re levant to host system software that interacts with s25fl116k memory devices. 7. address space maps 7.1 overview many commands operate on the main flash memory array. some commands operate on address spaces separate from the main flash array. each separate address space uses the full 24-bit address but may only define a small portion of the available address space. 7.2 flash memory array the main flash array is divided into erase units call ed sectors. the sectors are uniform 4 kbytes in size. note: this is condensed table that use a couple of sectors as referenc es. there are address ranges that are not explicitly listed. al l 4-kb sectors have the pattern xxx000h-xxxfffh. 7.3 security registers the s25fl116k provides four 256-byte security registers. each register can be used to store information that can be permanently protecte d by programming one time programmable (otp) lock bits in status register-2. register 0 is used by spansion to store and protect the serial flash discoverable parameters (sfdp) information that is also accessed by the read sfdp command. the three additional security registers can be eras ed, programmed, and protected individually. these registers may be used by system manu facturers to store and permanently pr otect security or other important information separate from the main memory array. 7.3.1 security register 0 - serial flash discover able parameters (sfdp) the s25fl116k features a 256-byte se rial flash discoverable parameter (sfdp) space, located in security register-0, that contains information about the device o perational capabilities such as available commands, timing and other features. the sfdp parameters are st ored in one or more parameter identification (pid) tables. currently only one pid table is specified but more may be added in the future. the read sfdp register command reads the contents of security regi ster-0 and is compatible with the jedec jesd216 sfdp standard. table 7.1 s25fl116k main memory address map sector size (kbyte) sector count sector range address range (byte address) notes 4 512 sa0 000000h-000fffh sector starting address ? sector ending address : : sa511 1ff000h-1fffffh table 7.2 security register addresses security register address 0 (sfdp) 000000h - 0000ff 1 001000h - 0010ff 2 002000h - 0020ff 3 003000h - 0030ff
42 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) table 7.3 serial flash discoverable parameter definition table (sheet 1 of 2) dword byte address data description comment sfdp header 1 00h 53h sfdp signature sfdp signature = 50444653h 01h 46h sfdp signature 02h 44h sfdp signature 03h 50h sfdp signature sfdp header 2 04h 00h sfdp minor revisions sfdp revision 1.0 05h 01h sfdp major revisions 06h 02h number of parameter headers (nph) 3 parameter headers 07h ffh reserved parameter header 1 08h 00h pid(0): parameter id (1) mandatory jedec parameter = 00h 09h 00h pid(0): jedec parameter minor revisions jedec parameter version 1.0 as published in jesd216 april 2011 0ah 01h pid(0): jedec parameter major revisions 0bh 09h pid(0): jedec parameter length 9 dwords parameter header 2 0ch 80h pid(0): address of parameter table (a7-a0) pid(0) table address = 000080h 0dh 00h pid(0): address of parameter table (a15-a8) 0eh 00h pid(0): address of parameter table (a23-a16) 0fh ffh reserved parameter header 3 10h efh pid(1): parameter id legacy parameter id = efh 11h 00h pid(1): parameter minor revisions serial flash basics version 1.0 12h 01h pid(1): parameter major revisions 13h 04h pid(1): parameter length 4 dwords parameter header 4 14h 80h pid(1): address of parameter table (a7-a0) pid(1) table address = 000080h same data as first 4 words of jedec parameter 15h 00h pid(1): address of parameter table (a15-a8) 16h 00h pid(1): address of parameter table (a23-a16) 17h ffh reserved parameter header 5 18h 01h pid(2): parameter id spansion manufacturer id = 01h 19h 00h pid(2): serial flash properties minor revisions spansion serial flash properties revision 1.0 1ah 01h pid(2): serial flash properties major revisions 1bh 00h pid(2): parameter length 00h = not implemented parameter header 6 1ch a4h pid(2): address of parameter table (a7-a0) pid(2) table address = 0000a4h 1dh 00h pid(2): address of parameter table (a15-a8) 1eh 00h pid(2): address of parameter table (a23-a16) 1fh ffh reserved reserved 20h to 7fh ffh reserved jedec flash parameters 1 80h e5h bits 7:5 = unused = 111b bits 4:3 = target flash has nonvolatile status bit and does not require status register to be written on every power on to allow writes and erases = 00b bit 2 = program buffer > 64 bytes = 1 bits 1:0 = uniform 4-kb erase = 01b start of sfdp jedec parameter 81h 20h 4 kbyte erase opcode 82h f1h bit[7] = 1 reserved bit[6] = 1 supports quad out read (1-1-4) bit[5] = 1 supports quad i/o read (1-4-4) bit[4] = 1 supports dual i/o read (1-2-2) bit[3] = 0 dual transfer rate not supported bit[2:1] = 00 3-byte / 24-bit addressing bit[0] = 1 supports single input dual output read command support 83h ffh reserved
november 6, 2013 s25fl116k_00_06 s25fl116k 43 data sheet (preliminary) note: 1. pid(x) = parameter identification table (x). jedec flash parameters 2 84h ffh 16 megabits = 00ffffffh 32 megabits = 01ffffffh 64 megabits = 02ffffffh flash size in bits 85h ffh 86h ffh 87h 00h / 01h / 02h jedec flash parameters 3 88h 44h bit[7:5] = 010 2 cycles of mode bits are needed bit[4:0] = 00100 4 dummy cycles are needed fast read quad i/o default setting 89h ebh (1-4-4) quad i/o fast read opcode 8ah 08h bit[7:5] = 000 no mode cycles are needed bit[4:0] = 01000 8 dummy cycles are needed fast read quad output default setting 8bh 6bh (1-1-4) quad output fast read opcode jedec flash parameters 4 8ch 08h bit[7:5] = 000 no mode cycles are needed bit[4:0] = 01000 8 dummy cycles are needed fast read dual output default setting 8dh 3bh (1-1-2) dual output fast read opcode 8eh 80h bit[7:5] = 100 4 mode cycles are needed bit[4:0] = 00000 no dummy cycles are needed fast read dual i/o default setting 8fh bbh (1-2-2) dual i/o fast read opcode jedec flash parameters 5 90h eeh bit[31:5]= 1 reserved bit[4] = 0 (4-4-4) quad all read not supported bit[3:1] = 1 reserved bit[0] = 0 (2-2-2) dual all read not supported uniform width protocol support 91h ffh 92h ffh 93h ffh jedec flash parameters 6 94h ffh reserved dual all read parameters reserved 95h ffh reserved 96h ffh bit[7:5] = 111 mode cycles needed bit[4:0] = 11111 dummy cycles needed 97h ffh (2-2-2) dual all read command not supported = ffh jedec flash parameters 7 98h ffh reserved quad all read parameters reserved 99h ffh reserved 9ah ffh bit[7:5] = 111 mode cycles needed bit[4:0] = 11111 dummy cycles needed 9bh ffh (4-4-4) quad all read command not supported = ffh jedec flash parameters 8 9ch 0ch sector type 1 size 2 n bytes = 4 kb = 0ch sector / block architecture 9dh 20h sector type 1 instruction 9eh 10h sector type 2 size 2 n bytes = 64 kb = 10h 9fh d8h sector type 2 instruction jedec flash parameters 9 a0h 00h sector type 3 size 2 n bytes = not supported = 00h a1h ffh sector type 3 instruction = not supported = ffh a2h 00h sector type 4 size 2 n bytes = not supported = 00h a3h ffh sector type 4 instruction = not supported = ffh a4h to f7h ffh reserved f8h to ffh ffh unique id unique id table 7.3 serial flash discoverable parameter definition table (sheet 2 of 2) dword byte address data description comment
44 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 7.4 status registers status register-1 (sr1) and status register-2 (sr2) ca n be used to provide status on the availability of the flash memory array, if the device is write enabled or disabled, the state of write protection, quad spi setting, and security register lock status, and erase / program suspend status. sr1 and sr2 contain non-volatile bits in locations sr1[ 7:2] and sr2[6:0] that cont rol sector protection, otp register protection, status register protection, and quad mode. bit locations sr 2[7], sr1[1], and sr1[0] are read only volatile bits for write enable, and busy status; these are up dated by the memory control logic. the sr1[1] write enable bit is set only by the wr ite enable (06h) command and cleared by the memory control logic when an embedded operation is completed. write access to the non-volatile status register bits is controlled by the state of the non-volatile status register protect bits sr1[7] and sr2[0] (srp0, sr p1), the write enable comma nd (06h) preceding a write status registers command, and while quad mode is not enabled, the wp# pin. a volatile version of bits sr2[6], sr2[1], and sr1[7:2] that control sector protec tion and quad mode are used to control the behavior of these feat ures after power up. during power up these volatile bits are loaded from the non-volatile version of the status register bits. the write enable for volat ile status register (50h) command can be used to write these volatile bits when t he command is followed by a write status registers (01h) command. this gives more flexibility to chan ge the system configuration and memory protection schemes quickly without waiting for the typical non-volat ile bit write cycles or affecting the endurance of the status register non-volatile bits. write access to the volatile sr1 and sr2 status register bits is controlled by the state of the non-volatile status register protect bits sr1[7] and sr2[0] (srp0, srp1), the write enable for volatile status register command (50h) preceding a write status registers co mmand, and while quad mode is not enabled, the wp# pin. status register-3 (sr3) is used to configure and prov ide status on the variable read latency, and quad io wrapped read features. write access to the volatile sr3 status register bits is controlled by writ e enable for volatile status register command (50h) preceding a write status register command. the srp bits do not protect sr3. table 7.4 status register-1 (sr1) bits field name function type default state description 7srp0 status register protect 0 non-volatile and volatile versions 0 0 = wp# input has no effect or power supply lock down mode 1 = wp# input can protect the status register or otp lock down see table 7.9 on page 49 . 6sec sector / block protect 0 0 = bp2-bp0 protect 64-kb blocks 1 = bp2-bp0 protect 4-kb sectors see table 7.7 and table 7.8 for protection ranges. 5tb top / bottom protect 0 0 = bp2-bp0 protect from the top down 1 = bp2-bp0 protect from the bottom up see table 7.7 and table 7.8 for protection ranges 4bp2 block protect bits 0 000b = no protection see table 7.7 and table 7.8 for protection ranges. 3bp1 0 2bp0 0 1wel write enable latch volatile, read only 0 0 = not write enabled, no embedded operation can start 1 = write enabled, embedded operation can start 0busy embedded operation status volatile, read only 0 0 = not busy, no embedded operation in progress 1 = busy, embedded operation in progress
november 6, 2013 s25fl116k_00_06 s25fl116k 45 data sheet (preliminary) note: 1. lb0 value should be considered don't care for read. this bit is set to 1. 7.4.1 busy busy is a read only bit in the status register (sr1[0]) that is set to a 1 state when the device is executing a page program, sector erase, block erase, chip erase, write status registers or erase / program security register command. during this time the device will ignore further commands except for the read status register and erase / program suspend command (see t w , t pp , t se , t be , and t ce in section 5.7, ac electrical characteristics on page 31 ). when the program, erase or the write status / security register command has completed, the busy bit will be cleared to a 0 state in dicating the device is ready for further commands. table 7.5 status register-2 (sr2) bits field name function type default state description 7sus suspend status volatile, read only 0 0 = erase / program not suspended 1 = erase / program suspended 6cmp complement protect non-volatile and volatile versions 0 0 = normal protection map 1 = inverted protection map see table 7.7 and table 7.8 for protection ranges. 5lb3 security register lock bits otp 0 otp lock bits 3:0 for security registers 3:0 0 = security register not protected 1 = security register protected security register 0 contains the serial flash discoverable parameters and is always programmed and locked by spansion. 4lb2 0 3lb1 0 2lb0 (1) 1 1 qe quad enable non-volatile and volatile versions 0 0 = quad mode not enabled, the wp# pin and hold# are enabled 1 = quad mode enabled, the io2 and io3 pins are enabled, and wp# and hold# functions are disabled 0srp1 status register protect 1 0 0 = srp1 selects whether wp# input has effect on protection of the status register 1 = srp1 selects power supply lock down or otp lock down mode see table 7.9 on page 49 . table 7.6 status register-3 (sr3) bits field name function type default state description 7 rfu reserved 0 reserved for future use 6w6 burst wrap length volatile 1 00 = 8-byte wrap. data read starts at the initial address and wraps within an aligned 8-byte boundary 01 = 16-byte wrap. data read starts at the initial address and wraps within an aligned 16-byte boundary. 10 = 32-byte wrap. data read starts at the initial address and wraps within an aligned 32-byte boundary. 11 = 64-byte wrap. data read starts at the initial address and wraps within an aligned 64-byte boundary. 5w5 1 4w4 burst wrap enable 1 0 = wrap enabled 1 = wrap disabled 3 latency control (lc) variable read latency control 0 defines the number of read la tency cycles in fast read, dual out, quad out, dual io, and quad io commands. binary values for 1 to 15 latency cycles. a value of zero disables the variable latency mode. 20 10 00
46 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 7.4.2 write enab le latch (wel) write enable latch (wel) is a read only bit in the status register (sr1[1]) that is set to 1 after executing a write enable command. the wel status bit is cleared to 0 when the device is write disabled. a write disable state occurs upon power-up or after any of the foll owing commands: write disab le, page program, sector erase, block erase, chip erase, write status regist ers, erase security register and program security register. the wel status bit is cleared to 0 even w hen a program or erase operation is prevented by the block protection bits. the wel status bit is also cleared to 0 when a program or erase operation is suspended. the wel status bit is set to 1 when a program or erase operation is resumed. 7.4.3 block protect bits (bp2, bp1, bp0) the block protect bits (bp2, bp1, bp0) ar e non-volatile read / write bits in t he status register (sr1[4:2]) that provide write protection cont rol and status. block protect bits can be set using the write status registers command (see t w in section 5.7, ac electrical characteristics on page 31 ). all, none or a portion of the memory array can be protected from program and erase commands (see section 7.4.7, block protection maps on page 47 ). the factory default setting for the block protection bits is 0 (none of the array is protected.) 7.4.4 top / bottom block protect (tb) the non-volatile top / bottom bit (tb sr1[5]) controls if the block protect bits (bp2, bp1, bp0) protect from the top (tb=0) or the bottom (tb=1) of the array as shown in section 7.4.7, block protection maps on page 47 . the factory default setting is tb=0. the tb bi t can be set with the write status registers command depending on the state of the srp0, srp1 and wel bits. 7.4.5 sector / bl ock protect (sec) the non-volatile sector / block protect bit (sec sr1[6] ) controls if the block protect bits (bp2, bp1, bp0) protect either 4-kb sectors (sec=1) or 64-kb blocks (sec =0) in the top (tb=0) or the bottom (tb=1) of the array as shown in section 7.4.7, block protection maps on page 47 . the default setting is sec=0. 7.4.6 complement protect (cmp) the complement protect bit (cmp sr2[ 6]) is a non-volatile read / write bit in the status register (sr2[6]). it is used in conjunction with sec, tb, bp2, bp1 and bp0 bits to provide more flexibilit y for the array protection. once cmp is set to 1, previous array protection set by sec, tb, bp2, bp1 and bp0 will be reversed. for instance, when cmp=0, a top 4-kb sector can be protect ed while the rest of the array is not; when cmp=1, the top 4-kb sector will become unprotected while the rest of the array become read-only. please refer to section 7.4.7, block protection maps on page 47 for details. the default setting is cmp=0.
november 6, 2013 s25fl116k_00_06 s25fl116k 47 data sheet (preliminary) 7.4.7 block protection maps notes: 1. x = don?t care. 2. if any erase or program command specifies a memory region th at contains protected data portion, this command will be ignored. table 7.7 fl116k block protection (cmp = 0) status register (1) s25fl116k (16 mbit) block protection (cmp=0) (2) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion x x 0 0 0 none none none none 0 0 0 0 1 31 1f0000h ? 1fffffh 64 kb upper 1/32 0 0 0 1 0 30 and 31 1e0000h ? 1fffffh 128 kb upper 1/16 0 0 0 1 1 28 thru 31 1c0000h ? 1fffffh 256 kb upper 1/8 0 0 1 0 0 24 thru 31 180000h ? 1fffffh 512 kb upper 1/4 0 0 1 0 1 16 thru 31 100000h ? 1fffffh 1 mb upper 1/2 0 1 0 0 1 0 000000h ? 00ffffh 64 kb lower 1/32 0 1 0 1 0 0 and 1 000000h ? 01ffffh 128 kb lower 1/16 0 1 0 1 1 0 thru 3 000000h ? 03ffffh 256 kb lower 1/8 0 1 1 0 0 0 thru 7 000000h ? 07ffffh 512 kb lower 1/4 0 1 1 0 1 0 thru 15 000000h ? 0fffffh 1 mb lower 1/2 x x 1 1 x 0 thru 31 000000h ? 1fffffh 2 mb all 1 0 0 0 1 31 1ff000h ? 1fffffh 4 kb upper 1/512 1 0 0 1 0 31 1fe000h ? 1fffffh 8 kb upper 1/256 1 0 0 1 1 31 1fc000h ? 1fffffh 16 kb upper 1/128 1 0 1 0 x 31 1f8000h ? 1fffffh 32 kb upper 1/64 1 1 0 0 1 0 000000h ? 000fffh 4 kb lower 1/512 1 1 0 1 0 0 000000h ? 001fffh 8 kb lower 1/256 1 1 0 1 1 0 000000h ? 003fffh 16 kb lower 1/128 1 1 1 0 x 0 000000h ? 007fffh 32 kb lower 1/64
48 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) notes: 1. x = don?t care. 2. if any erase or program command specifies a memory region th at contains protected data portion, this command will be ignored. table 7.8 fl116k block protection (cmp = 1) status register (1) s25fl116k (16 mbit) block protection (cmp=1) (2) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion x x 0 0 0 0 thru 31 000000h ? 1fffffh all all 0 0 0 0 1 0 thru 30 000000h ? 1effffh 1,984 kb lower 31/32 0 0 0 1 0 0 thru 29 000000h ? 1dffffh 1,920 kb lower 15/16 0 0 0 1 1 0 thru 27 000000h ? 1bffffh 1,792 kb lower 7/8 0 0 1 0 0 0 thru 23 000000h ? 17ffffh 1,536 kb lower 3/4 0 0 1 0 1 0 thru 15 000000h ? 0fffffh 1 mb lower 1/2 0 1 0 0 1 1 thru 31 010000h ? 1fffffh 1,984 kb upper 31/32 0 1 0 1 0 2 and 31 020000h ? 1fffffh 1,920 kb upper 15/16 0 1 0 1 1 4 thru 31 040000h ? 1fffffh 1,792 kb upper 7/8 0 1 1 0 0 8 thru 31 080000h ? 1fffffh 1,536 kb upper 3/4 0 1 1 0 1 16 thru 31 100000h ? 1fffffh 1 mb upper 1/2 x x 1 1 x none none none none 1 0 0 0 1 0 thru 31 000000h ? 1fefffh 2,044 kb lower 511/512 1 0 0 1 0 0 thru 31 000000h ? 1fdfffh 2,040 kb lower 255/256 1 0 0 1 1 0 thru 31 000000h ? 1fbfffh 2,032 kb lower 127/128 1 0 1 0 x 0 thru 31 000000h ? 1f7fffh 2,016 kb lower 63/64 1 1 0 0 1 0 thru 31 001000h ? 1fffffh 2,044 kb upper 511/512 1 1 0 1 0 0 thru 31 002000h ? 1fffffh 2,040 kb upper 255/256 1 1 0 1 1 0 thru 31 004000h ? 1fffffh 2,032 kb upper 127/128 1 1 1 0 x 0 thru 31 008000h ? 1fffffh 2,016 kb upper 63/64
november 6, 2013 s25fl116k_00_06 s25fl116k 49 data sheet (preliminary) 7.4.8 status register protect (srp1, srp0) the status register protect bits (srp 1 and srp0) are non-volatile read / write bits in the status register (sr2[0] and sr1[7]). the srp bits c ontrol the method of write protecti on: software protection, hardware protection, power supply lock-down, or one time programmable (otp) protection. notes: 1. when srp1, srp0 = (1, 0), a power-down, power-up cycle will change srp1, srp0 to (0, 0) state. 2. the one time program feature is available upon special order. please contact spansion for details. 3. busy, wel, and sus (sr1[1:0] and sr2[7]) are volatile read only status bits that are never affected by the write status regis ters command. 4. the non-volatile version of cmp, qe, srp1, srp0, sec, tb, and bp2-bp0 (sr2[6,1,0] and sr1[6:2]) bits and the otp lb3-lb0 bits are not writable when protected by the srp bits and wp# as shown in the table. the non-volatile version of these status register bi ts are selected for writing when the write enable (06h) command precedes the write status registers (01h) command. 5. the volatile version of cmp, qe, srp1, srp0, sec, tb, and bp2-bp0 (sr2[6,1,0] and sr1[6:2]) bits are not writable when protec ted by the srp bits and wp# as shown in the table. the volatile versi on of these status register bits are selected for writing when th e write enable for volatile status register (50h) command precedes the wr ite status registers (01h) command. there is no volatile versi on of the lb3-lb0 bits and these bits are not affected by a volatile write status registers command. 6. the volatile sr3 bits are not protected by the srp bits and may be written at any time by volatile (50h) write enable command preceding the write status registers (01h) command. 7.4.9 erase / program suspend status (sus) the suspend status bit is a read only bi t in the status register (sr2[7]) th at is set to 1 after executing an erase / program suspend (75h) command . the sus status bit is cleared to 0 by erase / program resume (7ah) command as well as a power-down, power-up cycle. 7.4.10 security regi ster lock bits (lb3, lb2, lb1, lb0) the security register lock bits (lb3, lb2, lb1, lb0) are non-volatile one time program (otp) bits in status register (sr2[5:2]) that pr ovide the write protect control and stat us to the security registers. the default state of lb[3:1] is 0, securi ty registers 1 to 3 are unlocked. lb[3:1] can be set to 1 individually using the write status registers command. lb[3:1] are one time programmable (otp), once it?s set to 1, the corresponding 256-byte security register will become read-only permanently. security register 0 is programmed with the sfdp pa rameters and lb0 is programmed to 1 by spansion. 7.4.11 quad enable (qe) the quad enable (qe) bit is a non-volatile read / write bi t in the status register (s r2[1]) that allows quad spi operation. when the qe bit is set to a 0 stat e (factory default), the wp# pin and hold# are enabled. when the qe bit is set to a 1, the quad io2 and io3 pins are enabled, and wp# and hold# functions are disabled. note : if the wp# or hold# pins are tied directly to the power supply or ground during standard spi or dual spi operation, the qe bit should never be set to a 1. table 7.9 status register protection bits srp1 srp0 wp# status register description 0 0 x software protection wp# pin has no control. sr1 and sr2 can be written to after a write enable command, wel=1. [factory default] 0 1 0 hardware protected when wp# pin is low the sr1 and sr2 are locked and can not be written. 0 1 1 hardware unprotected when wp# pin is high sr1 and sr2 are unlocked and can be written to after a write enable command, wel=1. 10x power supply lock- down sr1 and sr2 are protected and can not be written to again until the next power-down, power-up cycle. (1) 1 1 x one time program (2) sr1 and sr2 are permanently protected and can not be written.
50 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 7.4.12 latency control (lc) status register-3 provides bi ts (sr3[3:0]) to select the number of r ead latency cycles used in each fast read command. the read data command is not affected by the latency code. the binary value of this field selects from 1 to 15 latency cycles. the zero value selects th e legacy number of late ncy cycles used in prior generation fl-k family devices. t he default is 0 cycles to provide ba ckward compatibility to legacy devices. the latency control bits may be set to select a number of read cycles optimized for the frequency in use. if the number of latency cycles is not sufficient fo r the operating frequency, invalid data will be read. notes: 1. sck frequency > 108 mhz sio, 108 mhz dio, or 108 mh z qio is not supported by this family of devices. 2. the dual i/o and quad i/o command protocols include continuous read mode bits following the address. the clock cycles for the se bits are not counted as part of the latency cycles shown in the table. example: the legacy dual i/o command has 4 continuous read mo de bits following the address and no additional dummy cycles. therefor e, the legacy dual i/o command without additional read laten cy is supported only up to the frequency shown in the table for a read latency of 0 cycles. by increasing the variable read latency t he frequency of the dual i/o command can be increased to allow operation up to the maximum supported 108 mhz dio frequency. 7.4.13 burst wrap enable (w4) status register-3 provides a bit (sr3[4]) to enable a read with wrap option for the quad i/o read command. when sr3[4]=1, the wrap mode is not enabled and unlim ited length sequential read is performed. when sr3[4]=0, the wrap mode is enabled and a fixed length and aligned group of 8, 16, 32, or 64 bytes will be read starting at the byte address provided by the q uad i/o read command and wrapping around at the group alignment boundary. 7.4.14 burst wrap length (w6, w5) status register-3 provides bits (s r3[1:0]) to select the alignment boundary at which reading will wrap to perform a cache line fill. reading begins at the initial byte address of a fast read quad io command, then sequential bytes are read until the se lected boundary is reached. reading then wraps to the beginning of the selected boundary. this enables critical word first cac he line refills. the wrap point can be aligned on 8-, 16-, 32-, or 64-byte boundaries. table 7.10 latency cycles versus frequency latency control read command maximum frequency (mhz) fast read dual output dual i/o quad output quad i/o 0 (legacy read latency) 108 (8 dummy) 108 (8 dummy) 88 (4 mode, 0 dummy) 108 (8 dummy) 78 (2 mode, 4 dummy) 1 5050944349 2 95 85 105 56 59 3 105 95 108 70 69 4 108 105 108 83 78 5 108 108 108 94 86 6 108 108 108 105 95 7 108 108 108 108 105 8 108 108 108 108 108 9 108 108 108 108 108 10 108 108 108 108 108 11 108 108 108 108 108 12 108 108 108 108 108 13 108 108 108 108 108 14 108 108 108 108 108 15 108 108 108 108 108
november 6, 2013 s25fl116k_00_06 s25fl116k 51 data sheet (preliminary) 7.5 device identification 7.5.1 legacy device identification commands three legacy commands are supported to access device i dentification that can indi cate the manufacturer, device type, and capacity (density). the returned data bytes provide the information as shown in table 7.11 . note: 1. the 90h instruction is followed by an address. address = 0 selects manufacturer id as the first returned data as shown in the table. address = 1 selects device id as the first returned data followed by manufacturer id. 7.5.2 serial flash discoverable parameters (sfdp) a read sfdp (5ah) command to read a jedec standard (jesd216) defined device information structure is supported. the information is stored in security register 0 and described in security register 0 - serial flash discoverable parameters (sfdp) on page 41 . table 7.11 device identification device opn instruction data 1 data 2 data 3 s25fl116k abh device id = 14h - - 90h manufacturer id = 01h device id = 14h - 9fh manufacturer id = 01h device type = 40h capacity = 15h
52 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 8. functional description 8.1 spi operations 8.1.1 standard spi commands the s25fl116k is accessed through an spi compatible bu s consisting of four signals: serial clock (clk), chip select (cs#), serial data input (si) and serial data output (so). standard spi commands use the si input pin to serially write instructions, addresses or data to the device on the rising edge of clk. the so output pin is used to read data or status from the device on the falling edge clk. spi bus operation mode 0 (0,0) and 3 (1,1) are support ed. the primary difference between mode 0 and mode 3 concerns the normal stat e of the clk signal when the spi bus mast er is in standby and data is not being transferred to the serial flash. for mode 0, the clk si gnal is normally low on the falling and rising edges of cs#. for mode 3, the clk signal is normally high on the falling and rising edges of cs#. 8.1.2 dual spi commands the s25fl116k supports dual spi operation when using the ?fast read dual output (3bh)? and ?fast read dual i/o (bbh)? commands. these commands allow data to be transferred to or from the device at two to three times the rate of ordinary serial flash devic es. the dual spi read commands are ideal for quickly downloading code to ram upon power-up (code-shadowing) or for executing non-speed-critical code directly from the spi bus (xip). when using dual spi commands, the si and so pins become bidirectional i/o pins: io0 and io1. 8.1.3 quad spi commands the s25fl116k supports quad spi operation when usi ng the ?fast read quad output (6bh)?, and ?fast read quad i/o (ebh)? commands. these commands allow data to be transferred to or from the device four to six times the rate of ordinary serial flash. the qu ad read commands offer a si gnificant improvement in continuous and random access transfer rates allowing fa st code-shadowing to ram or execution directly from the spi bus (xip). when using quad spi commands the si and so pins become bidirectional io0 and io1, and the wp# and hold# pins become io2 and io3 respectively. quad spi commands require the non-volatile or volatile quad enable bit (qe) in status register-2 to be set. 8.1.4 hold function for standard spi and dual spi operations, the hold# (i o3) signal allows the device interface operation to be paused while it is actively selected (when cs# is lo w). the hold function may be useful in cases where the spi data and clock signals are shared with other devices. for example, if the page buffer is only partially written when a priority interrupt requires use of the spi bus, the hold function can save the state of the interface and the data in the buffer so programming co mmand can resume where it left off once the bus is available again. the hold function is only available for standard spi and dual spi operation, not during quad spi. to initiate a hold condition, the device must be selected with cs# low. a hold condition will activate on the falling edge of the hold# signal if the clk signal is already low. if the clk is not already low the hold condition will activate after the next falling edge of clk. the hold condition will terminate on the rising edge of the hold# signal if the clk signal is already low. if the clk is not already low the hold condition will terminate after the next falling edge of clk. during a hold condition, the serial data output, (so) or io0 and io1, are high impedance and serial da ta input, (si) or io0 an d io1, and serial clock (clk) are ignored. the chip select (cs#) signal should be kept active (low) for the full duration of the hold operation to avoid resetting the internal logic state of the device. 8.2 write protection applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data in tegrity. to address this concern, the s25fl116k provides several means to protect the data from inadvertent program or erase.
november 6, 2013 s25fl116k_00_06 s25fl116k 53 data sheet (preliminary) 8.2.1 write pr otect features ? device resets when v cc is below threshold ? time delay write disable after power-up ? write enable / disable commands and automat ic write disable after erase or program ? command length protection ? all commands that write, program or erase must complete on a byte boundary (cs# driven high after a full 8 bits have been clocked) otherwise the command will be ignored ? software and hardware write protec tion using status register control ? wp# input protection ? lock down write protection until next power-up ? one time program (otp) write protection ? write protection using the deep power-down command upon power-up or at power-down, the s25fl116k will maintain a reset condition while v cc is below the threshold value of vwi, (see figure 5.5, power-up timing and voltage levels on page 30 ). while reset, all operations are disabled and no commands are recognized. during power-up and after the v cc voltage exceeds vwi, all program and erase related comma nds are further disabled for a time delay of t puw . this includes the write enable, page progr am, sector erase, block erase, chip erase and the write status registers commands. note that the chip select pi n (cs#) must track the v cc supply level at power-up until the v cc -min level and t vsl time delay is reached. if needed a pull-up resistor on cs# can be used to accomplish this. after power-up the device is automatically placed in a write-disabled state with th e status register write enable latch (wel) set to a 0. a write enable co mmand must be issued before a page program, sector erase, block erase, chip erase or write status registers command will be accepted. after completing a program, erase or write command the wr ite enable latch (wel) is automatic ally cleared to a write-disabled state of 0. software controlled main flash array write protection is facilitated using the writ e status registers command to write the status register pr otect (srp0, srp1) and block prot ect (cmp, sec,tb, bp2, bp1 and bp0) bits. the bp method allows a portion as small as 4-kb sector or the entire memory array to be configured as read only. used in conjunction with the write protect (wp#) pin, changes to the status register can be enabled or disabled under hardware control. see status registers on page 44. for further information. additionally, the deep-power-down (dpd) command offe rs an alternative means of data protection as all commands are ignored during the dpd state, except for the release from deep-power-down (res abh) command. thus, preventing any progra m or erase during the dpd state. 8.3 status registers the read and write status registers commands can be used to provide status and control of the flash memory device.
54 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 9. commands the command set of the s25fl116k is fully controlled through the spi bus (see table 9.1 to table 9.3 on page 55 ). commands are initiated with the falling edge of ch ip select (cs#). the first byte of data clocked into the si input provides the instruct ion code. data on the si input is sampled on the rising edge of clock with most significant bit (msb) first. commands vary in length from a sing le byte to several bytes. each command begins with an instruction code and may be followed by ad dress bytes, a mode byte, read latency (dummy / don?t care) cycles, or data bytes. commands are completed with the rising edge of edge cs#. clock relative sequence diagrams for each command are included in the command descriptions. all r ead commands can be completed after any data bit. however, all commands that write, program or erase must complete on a byte boundary (cs# driven high after a full 8 bits have been clocked) otherwise the command will be ignored. this feature further protects the device from inadvertent writes. additionally, while the memory is being programmed or erased, all commands except for read status register and suspend commands will be ignored until the program or erase cycle has completed. when the status register is being written, all commands except for read status register will be ignored until the status regist er write operation has completed. notes: 1. data bytes are shifted with most significant bit first. byte fi elds with data in parenthesis ?()? indicate data being read fr om the device on the so pin. 2. status register contents will repeat c ontinuously until cs# terminates the command. 3. set burst with wrap input format to load sr3. see table 7.6 on page 45 . io0 = x, x, x, x, x, x, w4, x] io1 = x, x, x, x, x, x, w5, x] io2 = x, x, x, x, x, x, w6 x] io3 = x, x, x, x, x, x, x,x 4. when changing the value of any single bit, read all other bits and rewrite the same value to them. table 9.1 command set (configuration, st atus, erase, program commands (1) ) command name byte 1 (instruction) byte 2 byte 3 byte 4 byte 5 byte 6 read status register-1 05h sr1[7:0] (2)(4) read status register-2 35h sr2[7:0] (2)(4) read status register-3 33h sr3[7:0] (2) write enable 06h write enable for volatile status register 50h write disable 04h write status registers 01h sr1[7:0] sr2[7:0] sr3[7:0] set burst with wrap 77h xxh xxh xxh sr3[7:0] (3) page program 02h a23?a16 a15?a8 a7?a0 d7?d0 sector erase (4 kb) 20h a23?a16 a15?a8 a7?a0 block erase (64 kb) d8h a23?a16 a15?a8 a7?a0 chip erase c7h/60h erase / program suspend 75h erase / program resume 7ah
november 6, 2013 s25fl116k_00_06 s25fl116k 55 data sheet (preliminary) notes: 1. dual output data io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 2. dual input address io0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5, a3, a1, m7, m5, m3, m1 3. quad output data io0 = (d4, d0, ?..) io1 = (d5, d1, ?..) io2 = (d6, d2, ?..) io3 = (d7, d3, ?..) 4. quad input address io0 = a20, a16, a12, a8, a4, a0, m4, m0 io1 = a21, a17, a13, a9, a5, a1, m5, m1 io2 = a22, a18, a14, a10, a6, a2, m6, m2 io3 = a23, a19, a15, a11, a7, a3, m7, m3 5. fast read quad i/o data io0 = (x, x, x, x, d4, d0, ?..) io1 = (x, x, x, x, d5, d1, ?..) io2 = (x, x, x, x, d6, d2, ?..) io3 = (x, x, x, x, d7, d3, ?..) 6. this command is recommended when using the dual or quad ?continuous read mode? feature. see section 9.3.8 and section 9.3.9 on page 69 for more information. notes: 1. the device id will repeat continuously until cs# terminates the command. 2. see section 7.5.1, legacy device identification commands on page 51 for device id information. the 90h instruction is followed by an address. address = 0 selects manufacturer id as the first returned data as shown in the table. address = 1 selects device id as the first returned data followed by manufacturer id. table 9.2 command set (read commands) command name byte 1 (instruction) byte 2 byte 3 byte 4 byte 5 byte 6 read data 03h a23?a16 a15?a8 a7?a0 (d7?d0, ?) fast read 0bh a23?a16 a15?a8 a7?a0 dummy (d7?d0, ?) fast read dual output 3bh a23?a16 a15?a8 a7?a0 dummy (d7?d0, ?) (1) fast read quad output 6bh a23?a16 a15?a8 a7?a0 dummy (d7?d0, ?) (3) fast read dual i/o bbh a23?a8 (2) a7?a0, m7?m0 (2) (d7?d0, ?) (1) fast read quad i/o ebh a23?a0, m7?m0 (4) (x,x,x,x, d7?d0, ?) (5) (d7?d0, ?) (3) continuous read mode reset (6) ffh ffh table 9.3 command set (id, security commands) command name byte 1 (instruction) byte 2 byte 3 byte 4 byte 5 byte 6 deep power-down b9h release power down / device id abh dummy dummy dummy device id (1) manufacturer / device id (2) 90h dummy dummy 00h manufacturer device id jedec id 9fh manufacturer memory type capacity read sfdp register / read unique id number 5ah 00h 00h a7?a0 dummy (d7?d0, ?) read security registers (3) 48h a23?a16 a15?a8 a7?a0 dummy (d7?d0, ?) erase security registers (3) 44h a23?a16 a15?a8 a7?a0 program security registers (3) 42h a23?a16 a15?a8 a7?a0 d7?d0, ?
56 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 3. security register address: security register 0: a23-16 = 00h; a15-8 = 00h; a7-0 = byte address security register 1: a23-16 = 00h; a15-8 = 10h; a7-0 = byte address security register 2: a23-16 = 00h; a15-8 = 20h; a7-0 = byte address security register 3: a23-16 = 00h; a15-8 = 30h; a7-0 = byte address security register 0 is used to store the sfdp parameters and is always programmed and locked by spansion. 9.1 configuration and status commands 9.1.1 read status regist ers (05h), (35h), (33h) the read status register commands allow the 8-bit stat us registers to be read. the command is entered by driving cs# low and shifting the instruction code ?05h? for status register-1, ?35h? for status register-2, or 33h for status register-3, into the si pin on the rising edge of clk. the status r egister bits are then shifted out on the so pin at the falling edge of clk with most significant bit (msb) first as shown in figure 9.1 . the status register bits are shown in section 7.4, status registers on page 44 . the read status register-1 (05h) command may be used at any time, even while a program, erase, or write status registers cycle is in progress. this allows the busy status bit to be checked to determine when the operation is complete and if the device can accept an other command. the read status register-2 (35h), and read status registers (33h) may be used only when the device is in standby, not busy with an embedded operation. status registers can be read continuously as each re peated data output delivers the updated current value of each status register. example: using the instruction code ?05h? for read stat us register-1, the first output of eight bits may show the device is busy, sr1[0]=1. by continuing to hold cs# low, the updated value of sr1 will be shown in the next byte output. this repeated reading of sr1can continue until the system detects the busy bit has changed back to ready status in one of t he status bytes being read out. the read status register commands are completed by driving cs# high. figure 9.1 read status register command sequence diagram 9.1.2 write enable (06h) the write enable command ( figure 9.2 ) sets the write enable latch (wel) bi t in the status register to a 1. the wel bit must be set prior to every page program, sect or erase, block erase, chip erase, write status registers and erase / program security registers command. the write enable command is entered by driving cs# low, shifting the instruction code ?06h? into the data input (si) pin on the rising edge of clk, and then driving cs# high. figure 9.2 write enable (wren 06h) command sequence cs# sclk si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction status updated status cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
november 6, 2013 s25fl116k_00_06 s25fl116k 57 data sheet (preliminary) 9.1.3 write enable for vola tile status register (50h) the non-volatile status register bits described in section 7.4, status registers on page 44 can also be written to as volatile bits. during power up reset, the non -volatile status register bi ts are copied to a volatile version of the status register that is used during devi ce operation. this gives more flexibility to change the system configuration and memory protection schemes qui ckly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the st atus register non-volat ile bits. to write the volatile version of the status register bits, the write enable for volat ile status register (50h) command must be issued and immediately followed by the write status registers (01h) command. write enable for volatile status register command ( figure 9.3 ) will not set the write enable latch (wel) bit, it is only valid for the next following write status registers command, to change the volatile status register bit values. figure 9.3 write enable for volatile st atus register command sequence 9.1.4 write disable (04h) the write disable command resets the write enable latch (w el) bit in the status regi ster to a 0. the write disable command is entered by driving cs# low, shifting the instruction code ?04h? into the si pin and then driving cs# high. note that the wel bit is automati cally reset after power-up and upon completion of the write status registers, erase / prog ram security registers, page program, sector erase, block erase and chip erase commands. figure 9.4 write disable (wrdi 04h) command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
58 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 9.1.5 write status registers (01h) the write status registers command a llows the status regist ers to be written. only non-volatile status register bits srp0, sec, tb, bp2, bp1 , bp0 (sr1[7:2]) cmp, lb3, lb2, lb1, qe, srp1 (sr2[6:0]), and the volatile bits sr3[6:0] can be written. all other stat us register bit locations are read-only and will not be affected by the write status regist ers command. lb3-0 are non-volatile ot p bits; once each is set to 1, it can not be cleared to 0. the status register bits are shown in section 7.4, status registers on page 44 . any reserved bits should only be written to their default value. to write non-volatile status register bits, a stan dard write enable (06h) command must previously have been executed for the device to accept the write stat us registers command (status register bit wel must equal 1). once write enabled, the command is entered by driving cs# low, sending the instruction code ?01h?, and then writing the status register data bytes as illustrated in figure 9.5 . to write volatile status register bi ts, a write enable for volatile stat us register (50h) command must have been executed prior to the write st atus registers command (status regi ster bit wel remains 0). however, srp1 and lb3, lb2, lb1, lb0 can not be changed because of the otp pr otection for these bits. upon power off, the volatile stat us register bit values will be lost, and the non -volatile status register bit values will be restored when power on again. to complete the write status registers command, the cs # pin must be driven high after the eighth bit of a data value is clocked in (cs# must be driven high on an 8-bit boundary). if this is not done the write status registers command will not be executed. if cs# is driv en high after the eighth clock the cmp and qe bits will be cleared to 0 if the srp1 bit is 0. the sr2 bits are u naffected if srp1 is 1. if cs# is driven high after the eighth or sixteenth clock, the sr3 bits will not be affected. during non-volatile status register write operation (06h combined with 0 1h), after cs# is driven high at the end of the write status registers command, the self-timed write status registers operation will commence for a time duration of t w (see section 5.7, ac electrical characteristics on page 31 ). while the write status registers operation is in progress, the read status register command may still be accessed to check the status of the busy bit. the busy bit is a 1 during the write status register s operation and a 0 when the operation is finished and ready to accept other command s again. after the write status registers operation has finished, the write enable latch (wel) bit in the status register will be cleared to 0. during volatile status register writ e operation (50h combined with 01h), af ter cs# is driven high at the end of the write status registers command, the status register bits will be u pdated to the new values within the time period of t shsl2 (see section 5.7, ac electrical characteristics on page 31 ). busy bit will remain 0 during the status register bit refresh period. refer to section 7.4, status registers on page 44 for detailed status register bit descriptions. figure 9.5 write status registers command sequence diagram cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input status register-1 input status register-2 input status register-3
november 6, 2013 s25fl116k_00_06 s25fl116k 59 data sheet (preliminary) 9.2 program and erase commands 9.2.1 page program (02h) the page program command allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (ffh) memory locations. a write enable command must be ex ecuted before the device will accept the page program command (status register bi t wel= 1). the command is initiated by driving the cs# pin low then shifting the instruction code ?02h? fo llowed by a 24-bit address (a23-a0) and at least one data byte, into the si pin. the cs# pin must be held low for the entire length of the command while data is being sent to the device. the page pr ogram command sequence is shown in figure 9.6, page program command sequence on page 59 . if an entire 256-byte page is to be programmed, the last address byte (the 8 le ast significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. in some cases, less than 256 bytes (a partial page) can be programmed without havin g any effect on other bytes within the same page. one condition to perform a partial page program is that the number of clocks can not exceed the remaining page length. if more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase commands, the cs# pin must be driven high afte r the eighth bit of the last byte has been latched. if this is not done the page prog ram command will not be executed. after cs# is driven high, the self-timed page program command will commence for a time duration of t pp ( section 5.7, ac electrical characteristics on page 31 ). while the page program cycle is in progress, the read status register command may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other commands again. after the page program cycle has finish ed the write enable latch (wel) bit in the status register is cleared to 0. the page program command will not be executed if the addr essed page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits. figure 9.6 page program command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 23 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address input data 1 input data 2
60 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 9.2.2 sector erase (20h) the sector erase command sets all memory within a specif ied sector (4 kbytes) to the erased state of all 1?s (ffh). a write enable command must be executed befor e the device will accept the sector erase command (status register bit wel must equal 1). the command is initiated by driving the cs# pin low and shifting the instruction code ?20h? followed a 24-bit sector address (a23-a0) see supply and signal ground (v ss ) on page 16. the sector erase command sequence is shown in figure 9.7 on page 60 . the cs# pin must be driven high after t he eighth bit of the last byte has been latched. if this is not done the sector erase command will not be executed. after cs# is driven high, the self-tim ed sector erase command will commence for a time duration of t se . section 5.7, ac electrical characteristics on page 31 while the sector erase cycle is in progress, the read status r egister command may still be accessed for checking the status of the busy bit. the busy bit is a 1 during t he sector erase cycle and bec omes a 0 when the cycle is finished and the device is ready to accept ot her commands again. after the se ctor erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the sector erase command will not be executed if the addressed sector is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits. figure 9.7 sector erase command sequence 9.2.3 64-kb block erase (d8h) the block erase command sets all memory within a specif ied block (64 kbytes) to the erased state of all 1s (ffh). a write enable command must be executed before the device will accept the block erase command (status register bit wel must equal 1). the command is initiated by driving the cs# pin low and shifting the instruction code ?d8h? followed a 24-bit block address (a23-a0) see supply and signal ground (v ss ) on page 16. the block erase command sequence is shown in figure 9.8 . the cs# pin must be driven high after t he eighth bit of the last byte has been latched. if this is not done the block erase command will not be executed. after cs# is driven high, the self-t imed block erase command will commence for a time duration of t be (see section 5.7, ac electrical characteristics on page 31 ). while the block erase cycle is in progress, the read status register command may still be accessed for checking the status of the busy bit. the busy bit is a 1 du ring the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other commands again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase command will not be executed if the addressed sector is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits (see section 7.4, status registers on page 44 ). figure 9.8 64 kb block erase command sequence cs# sck si so phase 76 54321023 1 0 instruction address cs# sck si so phase 76 54321023 1 0 instruction address
november 6, 2013 s25fl116k_00_06 s25fl116k 61 data sheet (preliminary) 9.2.4 chip erase (c7h / 60h) the chip erase command sets all memory within the devi ce to the erased state of all 1?s (ffh). a write enable command must be executed before the device will accept the chip erase command (status register bit wel must equal 1). the command is initiated by dr iving the cs# pin low and shifting the instruction code ?c7h? or ?60h?. the chip erase command sequence is shown in figure 9.9 . the cs# pin must be driven high afte r the eighth bit has been latched. if this is not done the chip erase command will not be executed. after cs# is driven hi gh, the self-timed chip erase command will commence for a time duration of t ce ( section 5.7, ac electrical characteristics on page 31 ). while the chip erase cycle is in progress, the read status regi ster command may still be accessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cycle and becomes a 0 when finished and the device is ready to accept other commands again. after the chip erase cycl e has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip erase command will not be executed if any page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits (see section 7.4, status registers on page 44 ). figure 9.9 chip erase command sequence 9.2.5 erase / program suspend (75h) the erase / program suspend command allows the system to interrupt a sector or block erase operation, then read from or program data to any other sector. the erase / program suspend command also allows the system to interrupt a page program operation and then r ead from any other page or erase any other sector or block. the erase / program suspend command sequence is shown in figure 9.10, erase / program suspend command sequence on page 62 . the write status registers command (01h), program se curity registers (42h), and erase commands (20h, d8h, c7h, 60h, 44h) are not allowed during erase suspe nd. erase suspend is valid only during the sector or block erase operation. if written during the chip er ase operation, the erase suspend command is ignored. the write status registers command (01h), erase secu rity registers (44h), an d program commands (02h, 32h, 42h) are not allowed during program suspend. progr am suspend is valid only during the page program operation. cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
62 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) the erase / program suspend command 75h will be accepted by the device only if the sus bit in the status register equals to 0 and the busy bit equals to 1 while a sector or block erase or a page program operation is on-going. if the sus bit equals to 1 or the busy bi t equals to 0, the suspend command will be ignored by the device. program or erase command for the se ctor that is being suspended will be ignored. a maximum of time of t sus ( section 5.7, ac electrical characteristics on page 31 ) is required to suspend the erase or program operation. the busy bit in the stat us register will be cleared from 1 to 0 within t sus and the sus bit in the status register will be set from 0 to 1 immediately after erase / program suspend. for a previously resumed erase / program operation, it is also required that the suspend command 75h is not issued earlier than a minimum of time of t sus following the preceding resume command 7ah. unexpected power off during the erase / program su spend state will reset the device and release the suspend state. sus bit in the status register will also reset to 0. the data within the page, sector or block that was being suspended may become corrupted. it is recommended for the user to implement system design techniques to prevent accidental power interr uption, provide non-volatile tracking of in process program or erase commands, and preserve data integrit y by evaluating the non-volatile program or erase tracking information during each system power up in order to identify and repair (re-erase and re-program) any improperly terminated pr ogram or erase operations. figure 9.10 erase / program suspend command sequence table 9.4 commands accepted during suspend operation suspended command allowed instruction program or erase read data 03h program or erase fast read 0bh program or erase fast read dual output 3bh program or erase fast read quad output 6bh program or erase fast read dual i/o bbh program or erase fast read quad i/o ebh program or erase continuous read mode reset ffh program or erase read status register-1 05h program or erase read status register-2 35h program or erase write enable 06h erase page program 02h program sector erase 20h program block erase d8h program or erase erase / program resume 7ah cs# sck si so phase phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 suspend instruction read status instruction status instr. during suspend repeat status read until suspended tsus
november 6, 2013 s25fl116k_00_06 s25fl116k 63 data sheet (preliminary) 9.2.6 erase / program resume (7ah) the erase / program resume command ?7 ah? must be written to resume th e sector or block erase operation or the page program operation after an erase / pr ogram suspend. the resume command ?7ah? will be accepted by the device only if the sus bit in the stat us register equals to 1 and the busy bit equals to 0. after the resume command is issued the sus bit will be cleared from 1 to 0 immediately, the busy bit will be set from 0 to 1 within 200 ns and the sector or blo ck will complete the erase operation or the page will complete the program operation. if the sus bit equa ls to 0 or the busy bit equals to 1, the resume command ?7ah? will be ignored by the device. the erase / program resume command sequence is shown in figure 9.11 . it is required that a subsequent erase / program su spend command not to be issued within a minimum of time of ?t sus ? following a resume command. figure 9.11 erase / program resume command sequence 9.3 read commands 9.3.1 read data (03h) the read data command allows one or more data bytes to be sequentially read from the memory. the command is initiated by driving the cs# pin low and th en shifting the instruction code ?03h? followed by a 24-bit address (a23-a0) into the si pin. the code and address bits are la tched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memory location will be shifted out on the so pin at the falling edge of clk with most significant bit (msb) first. the address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single command as long as the clock continues. the command is co mpleted by driving cs# high. the read data command sequence is shown in figure 9.12 . if a read data command is issued while an erase, program or write cycle is in process (busy=1) the command is ignored and will not have any effects on the current cycle. the read data command allo ws clock rates from dc to a maximum of f r (see section 5.7, ac electrical characteristics on page 31 ). figure 9.12 read data command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sclk si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address data 1 data 2
64 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 9.3.2 fast read (0bh) the fast read command is similar to the read data co mmand except that it can operate at higher frequency than the traditional read data command. this is acco mplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 9.13 . the dummy clocks allow the devices in ternal circuits additional time for setting up the initial address. during the dummy clocks the data val ue on the si pin is a ?don?t care.? when variable read la tency is enabled, the number of dummy cycles is set by t he latency cont rol value in sr3 to optimize the latency for the frequency in use. see. table 7.10, latency cycles versus frequency on page 50 . figure 9.13 fast read command sequence 9.3.3 fast read dual output (3bh) the fast read dual output (3bh) command is similar to the standard fast read (0 bh) command except that data is output on two pins; io0 and io1. this allows dat a to be transferred from the s25fl116k at twice the rate of standard spi devices. the fast read dual ou tput command is ideal for quickly downloading code from flash to ram upon power-up or for applications that cache code-segments to ram for execution. similar to the fast read command, the fast read dual output command can operate at higher frequency than the traditional read data command. this is accomp lished by adding eight ?dummy? clocks after the 24- bit address as shown in figure 9.14 . the dummy clocks allow the device's internal circuits additional time for setting up the initial address. the inpu t data during the dummy clocks is ?d on?t care.? however, the io0 pin should be high-impedance prior to the fa lling edge of the first data out clock. when variable read la tency is enabled, the number of dummy cycles is set by t he latency cont rol value in sr3 to optimize the latency for the frequency in use. see. table 7.10, latency cycles versus frequency on page 50 . figure 9.14 fast read dual output command sequence cs# sclk si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1 cs# sclk io0 io1 phase 7 6 5 4 3 2 1 0 23 22 21 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 instruction address dummy data 1 data 2
november 6, 2013 s25fl116k_00_06 s25fl116k 65 data sheet (preliminary) 9.3.4 fast read quad output (6bh) the fast read quad output (6bh) command is similar to the fast read dual output (3bh) command except that data is output on four pins, io0, io1, io2, and io3. a quad enable of stat us register-2 must be executed before the device will accept the fast read quad outp ut command (status register bit qe must equal 1). the fast read quad output command allows data to be transferred from the s25fl116k at four times the rate of standard spi devices. the fast read quad output comm and can operate at higher frequency than the traditional read data command. this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 9.15 . the dummy clocks allow the device's internal circ uits additional time for setting up the initial address. the input data duri ng the dummy clocks is ?don?t care.? however, the io pins should be high- impedance prior to the falling edge of the first data out clock. when variable read la tency is enabled, the number of dummy cycles is set by t he latency cont rol value in sr3 to optimize the latency for the frequency in use. see. table 7.10, latency cycles versus frequency on page 50 . figure 9.15 fast read quad output command sequence cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 23 1 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 instruction address dummy d1 d2 d3 d4 d5
66 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 9.3.5 fast read dual i/o (bbh) the fast read dual i/o (bbh) command allows for improved random access while maintaining two io pins, io0 and io1. it is similar to the fast read dual output (3bh) command but with the capability to input the address bits (a23-0) two bits per clock. this reduced command overhead may allow for code execution (xip) directly from the dual spi in some applications. fast read dual i/o with ?continuous read mode? the fast read dual i/o command can further reduce instruction overhead through setting the ?continuous read mode? bits (m7-0) after the input address bits (a23-0), as shown in figure 9.16 . the upper nibble of the (m7-4) controls the length of the next fast read dual i/o command through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3-0) are don?t care (?x?). however, the io pins should be high-impedance prior to the falling edge of the first data out clock. if the ?continuous read mode? bits m5-4 = (1,0), th en the next fast read dual i/o command (after cs# is raised and then lowered) does not requir e the bbh instruction code, as shown in figure 9.17 . this reduces the command sequence by eight clocks and allows the read address to be immediately entered after cs# is asserted low. if the ?continuous read mode? bits m5-4 do not equal to (1,0), the next command (after cs# is raised and then lowered) requires the first byte inst ruction code, thus returning to normal operation. a ?continuous read mode? reset command can also be us ed to reset (m7-0) before issuing normal commands (see see continuous read mode reset (ffh or ffffh) on page 69. ). when variable read la tency is enabled, the number of latency (mode + dummy) cycl es is set by the latency control value in sr3 to optimize the latency for the frequency in use. see. table 7.10, latency cycles versus frequency on page 50 . note that the legacy read dual i/o command has four mode cycles and no dummy cycles for a total of four latency cycl es, enabling the variable read latency a llows for the additi on of more read latency to enable higher frequency operation of the dual i/o command. figure 9.16 fast read dual i/o command sequence (initial command or previous m5-4 10) note: 1. least significant 4 bits of mode are don?t care and it is op tional for the host to drive these bits. the host may turn off dr ive during these cycles to increase bus turn around time between mode bits from host and returning data from the memory. figure 9.17 fast read dual i/o command sequence (previous command set m5-4 = 10) cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 22 2 0 6 4 2 0 6 4 2 0 6 4 2 0 23 3 1 7 5 3 1 7 5 3 1 7 5 3 1 instruction address mode dummy data 1 data 2 cs# sck io0 io1 phase 6 4 2 0 22 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 23 3 1 7 5 3 1 7 5 3 1 7 5 3 1 data n address mode dummy data 1 data 2
november 6, 2013 s25fl116k_00_06 s25fl116k 67 data sheet (preliminary) 9.3.6 fast read quad i/o (ebh) the fast read quad i/o (ebh) command is similar to the fast read d ual i/o (bbh) command except that address and data bits are input and output through four pins io0, io1, io2 and io 3 and four dummy clock are required prior to the data output. th e quad i/o dramatically reduces in struction overhead allowing faster random access for code execution (xip) directly from the quad spi. the quad en able bit (qe) of status register-2 must be set to enable the fast read quad i/o command. fast read quad i/o with ?continuous read mode? the fast read quad i/o command can further reduce instruction overhead through setting the ?continuous read mode? bits (m7-0) after the input address bits (a23-0), as shown in figure 9.18, fast read quad i/o command sequence (initial command or previous m5-4 10) on page 67 . the upper nibble of the (m7-4) controls the length of the next fast read quad i/o command through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m 3-0) are don?t care (?x?). however, the io pins should be high-impedance prior to the falling edge of the first data out clock. if the ?continuous read mode? bits m5-4 = (1,0), then the next fast read quad i/o command (after cs# is raised and then lowered) does not requir e the ebh instruction code, as shown in figure 9.19, fast read quad i/o command sequence (pre vious command set m5-4 = 10) on page 67 . this reduces the command sequence by eight clocks and allows the read address to be immediately entered after cs# is asserted low. if the ?continuous read mode? bits m5-4 do not equal to (1,0), the next command (after cs# is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. a ?continuous read mode? reset command can also be used to reset (m7-0) before issuing normal commands (see section 9.3.8, continuous read mode reset (ffh or ffffh) on page 69 ). when variable read la tency is enabled, the number of latency (mode + dummy) cycl es is set by the latency control value in sr3 to optimize the latency for the frequency in use. see. table 7.10, latency cycles versus frequency on page 50 . note that the legacy read quad i/o command has two mode cycles plus four dummy cycles for a total of six latency cycles, enabling the variable read latency allows for the addition of more read latency to enable higher frequency operation of the quad i/o command. figure 9.18 fast read quad i/o command sequence (initial command or previous m5-4 10) note: 1. least significant 4 bits of mode are don?t care and it is op tional for the host to drive these bits. the host may turn off dr ive during these cycles to increase bus turn around time between mode bits from host and returning data from the memory. figure 9.19 fast read quad i/o command sequence (previous command set m5-4 = 10) cs# sclk io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 20 4 0 4 0 4 0 4 0 4 0 4 0 21 5 1 5 1 5 1 5 1 5 1 5 1 22 6 2 6 2 6 2 6 2 6 2 6 2 23 7 3 7 3 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4 cs# sck io0 io1 io2 io3 phase 4 0 4 0 20 4 0 4 0 4 0 4 0 6 4 2 0 5 1 5 1 21 5 1 5 1 5 1 5 1 7 5 3 1 6 2 6 2 22 6 2 6 2 6 2 6 1 7 5 3 1 7 3 7 3 23 7 3 7 3 7 3 7 1 7 5 3 1 dn-1 dn address mode dummy d1 d2 d3 d4
68 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) fast read quad i/o with ?16/32/64-byte wrap around? the fast read quad i/o command can also be used to access a specific portion within a page by issuing a ?set burst with wrap? command prior to ebh. the ?s et burst with wrap? command can either enable or disable the ?wrap around? feature for the following ebh commands. when ?wrap around? is enabled, the data being accessed can be limited to either a 16/32/64-b yte section of data. the out put data starts at the initial address specified in the command, once it reache s the ending boundary of t he 16/32/64-byte section, the output will wrap around to the beginning boundary auto matically until cs# is pulled high to terminate the command. the burst with wrap feature allows a pplications that use cac he to quickly fetch a critical address and then fill the cache afterwards within a fixed length (16/32/64-byte s) of data without issuing multiple read commands. the ?set burst with wrap? command allows three ?wrap bits?, w6-4 to be set. the w4 bit is used to enable or disable the ?wrap around? operation while w6-5 are us ed to specify the length of the wrap around section within a page. see section 9.3.7, set burst with wrap (77h) on page 68 . 9.3.7 set burst with wrap (77h) the set burst with wrap (77h) command is used in conjunction with ?fast read quad i/o? commands to access a fixed length and alignment of 8/16/32/64-bytes of data. certain applications can benefit from this feature and improve the overall syst em code execution perf ormance. this command loads the sr3 bits. similar to a quad i/o command, the set burst with wrap co mmand is initiated by driving the cs# pin low and then shifting the instruction code ?77h? followed by 24-dummy bits and 8 ?wrap bits?, w7-0. the command sequence is shown in figure 9.20, set burst with wrap command sequence on page 68 . wrap bit w7 and the lower nibble w3-0 are not used. see status regi ster-3 (sr3[6:4]) for the encoding of w6-w4 in section 7.4, status registers on page 44 . once w6-4 is set by a set burst with wrap command, all the following ?fast read quad i/o? commands will use the w6-4 setting to access the 8/ 16/32/64-byte section of data. note, status register-2 qe bit (sr2[1]) must be set to 1 in order to use the fast read qu ad i/o and set burst with wrap commands. to exit the ?wrap around? function and return to normal read ope ration, another set burst with wrap command should be issued to set w4 = 1. the default value of w4 u pon power on is 1. in the case of a system reset while w4 = 0, it is recommended that the c ontroller issues a set burst with wrap command to reset w4 = 1 prior to any normal read commands since s25fl116k does not have a hardware reset pin. figure 9.20 set burst with wrap command sequence cs# sclk io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 .x .x .x .x .x .x w4 .x .x .x .x .x .x .x w5 .x .x .x .x .x .x .x w6 .x .x .x .x .x .x .x .x .x instruction don?t care wrap
november 6, 2013 s25fl116k_00_06 s25fl116k 69 data sheet (preliminary) 9.3.8 continuous read m ode reset (ffh or ffffh) the ?continuous read mode? bits are used in conjunc tion with ?fast read dual i/o? and ?fast read quad i/o? commands to provide the highest random flash memory access rate with minimum spi instruction overhead, thus allowing more efficient xip (execute in place) with this device family. the ?continuous read mode? bits m7-0 are set by the dual / quad i/o read commands. m5-4 are used to control whether the 8-bit spi instruction code (bbh or ebh) is needed or not for the next command. when m5-4 = (1,0), the next command will be treated the same as the current dual / quad i/o read command without needing the 8-bit instruction code; when m5-4 do not equal to (1,0), the devi ce returns to normal spi command mode, in which all commands can be accepted. m7 -6 and m3-0 are reserved bits for future use, either 0 or 1 values can be used. the continuous read mode reset command (ffh or ffff h) can be used to set m4 = 1, thus the device will release the continuous read mode and return to normal spi operation, as shown in figure 9.21 . figure 9.21 continuous read mode reset for fast read dual or quad i/o notes: 1. to reset ?continuous read mode? during quad i/o operation, only eight clocks are needed. the instruction is ?ffh?. 2. to reset ?continuous read mode? during dual i/o operat ion, sixteen clocks are needed to shift in instruction ?ffffh?. 9.3.9 host system reset commands since s25fl116k does not have a hardware reset pin, if the host system memory controller resets, without a complete power down and power up sequence, while an s25fl116k device is set to continuous mode read, the s25fl116k device will not re cognize any initial standard spi co mmands from the controller. to address this possibility, it is recommended to issu e a continuous read mode reset (ffffh) command as the first command after a system re set. doing so will release the devic e from the continuous read mode and allow standard spi commands to be recognized. see section 9.3.8, continuous read mode reset (ffh or ffffh) on page 69 . if burst wrap mode is used, it is also recommended to issue a set burst with wrap (77h) command that sets the w4 bit to one as the second command after a sys tem reset. doing so will release the device from the burst wrap mode and allow standard sequent ial read spi command operation. see section 9.3.7, set burst with wrap (77h) on page 68 . issuing these commands immediately after a non-power-cycle (warm) system reset, ensures the device operation is consistent with the power on default device operation. the same comm ands may also be issued after device power on (cold) reset so that syst em reset code is the same for warm or cold reset. cs# sck io0 io1 io2 io3 dio_phase qio_phase ffffh optional ffh mode bit reset for quad i/o optional ffh
70 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 9.4 id and security commands 9.4.1 deep-power-down (b9h) although the standby current during normal operation is re latively low, standby current can be further reduced with the deep-power-down command. the lower power consumption makes the deep-power-down (dpd) command especially useful for ba ttery powered applications (see i cc1 and i cc2 in section 5.7, ac electrical characteristics on page 31 ). the command is initiated by driving t he cs# pin low and shifting the instruction code ?b9h? as shown in figure 9.22 . the cs# pin must be driven high afte r the eighth bit has been latched. if this is not done the deep-power- down command will not be executed. after cs# is dr iven high, the power-down state will entered within the time duration of t dp ( section 5.7, ac electrical characteristics on page 31 ). while in the power-down state only the release from deep-power-down / device id command, which restores the device to normal operation, will be recognized. all other commands ar e ignored. this includes the read status register command, which is always available during normal operation. ignoring all but one command also makes the power down state a useful condition for securing maximum write protection. the device always powers-up in the normal operation with the standby current of i cc1 . figure 9.22 deep power-down command sequence cs# sclk si so phase 7 6 5 4 3 2 1 0 instruction
november 6, 2013 s25fl116k_00_06 s25fl116k 71 data sheet (preliminary) 9.4.2 release from deep-power -down / device id (abh) the release from deep-power-down / device id comm and is a multi-purpose comm and. it can be used to release the device from the deep-power-down state, or obtain the devices elec tronic identification (id) number. to release the device from the deep- power-down state, the command is i ssued by driving the cs# pin low, shifting the instruction code ?abh? and driving cs# high as shown in figure 9.23 . release from deep-power- down will take the time duration of t res1 ( section 5.7, ac electrical characteristics on page 31 ) before the device will resume normal operation and other command s are accepted. the cs# pin must remain high during the t res1 time duration. when used only to obtain the device id while not in the deep power-down state, t he command is initiated by driving the cs# pin low and shifting the instruction code ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first. the device id values for the s25fl116k is listed in section 7.5.1, legacy device identification commands on page 51 . the device id can be read continuously. the command is completed by driving cs# high. when used to release the device from the deep-power- down state and obtain the device id, the command is the same as previously described, and shown in figure 9.24 , except that after cs# is driven high it must remain high for a time duration of t res2 . after this time duration the device will resume normal operation and other commands will be accepted. if the release from deep-power-down / device id command is issued while an erase, program or write cyc le is in process (when busy equals 1) the command is ignored and will not have any effects on the current cycle. figure 9.23 release from deep-power-down command sequence figure 9.24 read electronic signature (res abh) command sequence cs# sclk si so phase 7 6 5 4 3 2 1 0 instruction cs# sck si so phase 7654321023 10 76543210 instruction (abh) dummy device id
72 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 9.4.3 read manufacturer / device id (90h) the read manufacturer / device id command is an alternative to the release from deep-power-down / device id command that provides both the jedec a ssigned manufacturer id and the specific device id. the read manufacturer / device id command is very similar to the release from deep-power-down / device id command. the command is initiated by driving the cs# pin low and shifting the instruction code ?90h? followed by a 24-bit address (a23-a0) of 000000h. after which, the manufacturer id and the device id are shifted out on the falling edge of clk with mo st significant bit (msb) first as shown in figure 9.25 . the device id values for the s25fl116k is listed in section 7.5.1, legacy device identification commands on page 51 . if the 24-bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the command is completed by driving cs# high. figure 9.25 read_id (90h) command sequence 9.4.4 read jedec id (9fh) for compatibility reasons, the s25fl11 6k provides several commands to elec tronically determine the identity of the device. the read jedec id command is comp atible with the jedec stan dard for spi compatible serial flash memories that was adopted in 2003. the command is initiated by driving the cs# pin low and shifting the instruction code ?9fh?. the jedec assig ned manufacturer id byte and two device id bytes, memory type (id15-id8) and capacity (id7-id0) are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 9.26 . for memory type and c apacity values refer to section 7.5.1, legacy device identification commands on page 51 . figure 9.26 read jedec id command sequence cs# sck si so phase 7654321023 10 7654321076543 210 instruction (90h) address manufacturer id device id cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data n
november 6, 2013 s25fl116k_00_06 s25fl116k 73 data sheet (preliminary) 9.4.5 read sfdp register / r ead unique id number (5ah) the read sfdp command is initiated by driving t he cs# pin low and shifting the instruction code ?5ah? followed by a 24-bit address (a23-a0) into the si pi n. eight ?dummy? clocks are also required before the sfdp register contents are shifted out on the falling edge of the 40th clk with most significant bit (msb) first as shown in figure 9.27 . for sfdp register values and descriptions, refer to table 7.3, serial flash discoverable parameter definition table on page 42 . note: a23-a8 = 0; a7-a0 are used to define the starti ng byte address for the 256-byte sfdp register. the 5ah command can also be used to access the read unique id number. this is a factory-set read-only 8-byte number that is unique to each s25fl1-k device . the id number can be used in conjunction with user software methods to help prevent copying or cloning of a system. figure 9.27 read sfdp register command sequence 9.4.6 erase security registers (44h) the erase security register command is similar to the sector erase command. a write enable command must be executed before the device will accept the eras e security register command (status register bit wel must equal 1). the command is initiated by driv ing the cs# pin low and shifting the instruction code ?44h? followed by a 24-bit address (a23-a0) to erase one of the security registers. note: 1. addresses outside the ranges in the table have undefined results. the erase security register command sequence is shown in figure 9.28 . the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the command will not be executed. after cs# is driven high, the self-t imed erase security register operation will commence for a time duration of t se (see section 5.7, ac electrical characteristics on page 31 ). while the erase security register cycle is in progress, the read status register command may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other commands again. after the erase security register cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the security register lock bits (lb3:1) in the status register-2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permanently locked, and an erase security register command to that register will be ignored (see security register lock bits (lb3, lb2, lb1, lb0) on page 49 ). figure 9.28 erase security registers command sequence cs# sclk si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1 address a23-16 a15-8 a7-0 security register-1 00h 10h xxh security register-2 00h 20h xxh security register-3 00h 30h xxh cs# sck si so phase 76 54321023 1 0 instruction address
74 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 9.4.7 program secur ity registers (42h) the program security register command is similar to the page program command. it allows from one byte to 256 bytes of security register data to be programm ed at previously erased (ffh) memory locations. a write enable command must be executed before the device will accept the program security register command (status register bit wel= 1). the command is initiated by driving the cs# pin low then shifting the instruction code ?42h? followed by a 24-bit address (a23-a0) and at least one data byte, into the si pin. the cs# pin must be held low for the entire length of the co mmand while data is being sent to the device. note: 1. addresses outside the ranges in the table have undefined results. the program security register command sequence is shown in figure 9.29 . the security register lock bits (lb3:1) in the status register-2 can be used to otp prot ect the security registers. on ce a lock bit is set to 1, the corresponding security register will be permanently locked, and a program security register command to that register will be ignored (see security register lock bits (lb3, lb2, lb1, lb0) on page 49 and page program (02h) on page 59 for detail descriptions). figure 9.29 program security registers command sequence address a23-16 a15-8 a7-0 security register-1 00h 10h byte address security register-2 00h 20h byte address security register-3 00h 30h byte address cs# sck si so phase 7 6 5 4 3 2 1 0 23 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address input data 1 input data 2
november 6, 2013 s25fl116k_00_06 s25fl116k 75 data sheet (preliminary) 9.4.8 read securit y registers (48h) the read security register command is similar to the fast read command and allows one or more data bytes to be sequentially read from one of the three security registers. the command is initiated by driving the cs# pin low and then shifting the instruction code ?48h? followed by a 24-bit address (a23-a0) and eight ?dummy? clocks into the si pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, a nd following the eight dummy cycles, the data byte of the addressed memory location will be shifted out on the so pin at the fal ling edge of clk with most significant bit (msb) first. locations with address bits a23-a16 not equal to ze ro, have undefined data. the byte address is automatically incremented to the next byte address after each byte of data is shifted out. once the byte address reaches the last byte of the register (byte ffh), it will reset to 00h, the first byte of the register, and continue to increment. the command is completed by driving cs# high. the read security register command sequence is shown in figure 9.30 . if a read security register command is issued while an erase, program, or write cycle is in process (busy=1), the command is ignored and will not ha ve any effects on the current cycle. the read security register comma nd allows clock rates from dc to a maximum of f r (see section 5.7, ac electrical characteristics on page 31 ). note: 1. addresses outside the ranges in the table have undefined results. figure 9.30 read security registers command sequence address a23-16 a15-8 a7-0 security register-0 (sfdp) 00h 00h byte address security register-1 00h 10h byte address security register-2 00h 20h byte address security register-3 00h 30h byte address cs# sclk si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1
76 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 10. data integrity 10.1 endurance the joint electron device engineering council (jed ec) standard jesd22-a117 defines the procedural requirements for performing valid endur ance and retention tests based on a qualification specification. this methodology is intended to determine the ability of a flash device to sustain repeated data changes without failure (program / erase endurance) and to retain dat a for the expected life (data retention). endurance and retention qualification specificati ons are specified in jesd47 or may be developed using knowledge-based methods as in jesd94. 10.1.1 erase endurance note: 1. data retention of 20 years is based on 1k erase cycles or less. 10.2 initial delivery state the device is shipped from spansion with non-vola tile bits / default states set as follows: ? the entire memory array is erased: i.e. all bits are set to 1 (each byte contains ffh). ? the unique device id is programmed to a random number seeded by the date and time of device test. ? the sfdp security register address spac e 0 contains the values as defined in table 7.3, serial flash discoverable parameter definition table on page 42 . security register address spaces 1 to 3 are erased: i.e. all bits are set to 1 (each byte contains ffh). ? status register-1 contains 00h. ? status register-2 contains 04h. ? status register-3 contains 70h. table 10.1 erase endurance parameter min typical unit erase per sector 100k cycle
november 6, 2013 s25fl116k_00_06 s25fl116k 77 data sheet (preliminary) ordering information 11. ordering part number the ordering part number is formed by a valid combination of the following: 11.1 valid combinations the valid combinations supported for this family. 12. contacting spansion obtain the latest list of company locations and contact information at http://www.spansion.com/about/pages/locations.aspx s25fl1 16 k 0x m f i 01 1 packing type 0 = tray 1 = tube 3 = 13? tape and reel model number (additional ordering options) 01 = 8-lead so package (208 mil) / 8-contact wson 02 = 5x5 ball bga package 03 = 4x6 ball bga package (208 mil) 04 = 8-lead so package (150 mil) temperature range i = industrial (?40c to +85c) v = automotive (?40c to +105c) package materials f = lead (pb)-free h = low-halogen, lead (pb)-free package type m = 8-lead so package n = 8-contact wson package b = 24-ball 6x8 mm bga package, 1.0 mm pitch speed 0x = 108 mhz device technology k = 90 nm floating gate process technology density 16 = 16 mbits device family s25fl1 spansion memory 3.0 volt-only, serial peripheral interface (spi) flash memory table 11.1 valid combinations base ordering part number speed option package and temperature model number packing type package marking fl116k 0x mfi 01 0, 1, 3 fl116kif01 04 fl116kif4 mfv 01 fl116kvf01 04 fl116kvf4 nfi 01 fl116kif01 nfv 01 fl116kvf01 bhi 02 0, 3 fl116kih02 03 fl116kih03 bhv 02 fl116kvh02 03 fl116kvh03
78 s25fl116k s25fl116k_00_06 november 6, 2013 data sheet (preliminary) 13. revision history section description revision 01 (january 11, 2013) initial release revision 02 (april 10, 2013) features updated cycling endurance information dc electrical characteristics u pdated the typical value of i cc1 and added max values for i cc1 and i cc2 ac electrical characteristics updated write stat us registers time and block erase time values data integrity added a paragraph updated erase endurance information removed data retention section revision 03 (august 26, 2013) global added erase / program suspend and erase / program resume features revision 04 (october 1, 2013) global promoted data sheet from advanc e information to preliminary replaced uson with wson dc electrical characteristics tabl e removed input and output capacitance revision 05 (october 16, 2013) features added the unique id security feature power-up timing and voltage levels ta b l e added v dd (low) time parameter serial flash discoverable parameter definition table modified parameter header 4 and jedec flash parameters 8 added byte address for unique id status register-2 (sr2) table corrected spri description command set (id, security commands) ta b l e added unique id to the list of security commands read sfdp register (5ah) modified the command name and added a paragraph revision 06 (november 6, 2013) global added automotive (?40c to +105c) temperature range
november 6, 2013 s25fl116k_00_06 s25fl116k 79 data sheet (preliminary) colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2013 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse?, ornand? and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. other names used are for informational purposes only and may be trademarks of their respective owners.

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